IP Library Granted Patent US 11,656,264
Granted Patent B2
US 11,656,264 · App. 17/374,119 · Granted May 23, 2023

High-speed signal subsystem testing system

Inventors: Umesh Chandra (Santa Cruz, CA); Bhyrav Mutnury (Austin, TX)
Assignee: Dell Products L.P.
G01R31/11G01M11/3109G01R31/083G01R31/68G06F17/142
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,656,264
App. No.
17/374,119
Granted
May 23, 2023
Kind
B2
Abstract

A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

Claims (44)

1. A high-speed signal subsystem testing system, comprising:

a processing system having a transmitter and a receiver;

a loop back subsystem coupled to each of the transmitter and the receiver to provide a testing communication path between the transmitter and the receiver that includes a plurality of different testing communication path portions; and

a communication path testing engine that is coupled to the transmitter and the receiver, wherein the communication path testing engine is configured to:

generate at least one test signal and transmit the at least one test signal via the transmitter and through the testing communication path provided by the loop back subsystem;

receive, in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path provided by the loop back subsystem;

process the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testing communication path;

compare the testing impedance profile for the testing communication path to an expected impedance profile and determine that at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path; and

generate and transmit, in response to determining that the at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path, a testing communication path issue communication.

2. The system of claim 1 , wherein the at least one test signal is provided by at least one step function and the at least one test signal result is provided by at least one reflection.

3. The system of claim 2 , wherein the at least one test signal is at least one Time-Domain Reflectometer (TDR) test signal and the at least one test signal result is at least one TDR reflection.

4. The system of claim 1 , wherein the processing of the at least one test signal result to generate the testing impedance profile for the testing communication path includes performing a Fast Fourier Transform (FFT) on the at least one test signal result to generate a transfer function, and generating the testing impedance profile for the testing communication path based on the transfer function.

5. The system of claim 1 , wherein the plurality of different testing communication path portions included in the testing communication path provided between the transmitter and the receiver by the loop back subsystem includes at least one processing system mounting element portion, at least one circuit board trace portion, at least one connector portion, and at least one cable portion.

6. The system of claim 1 , wherein the testing communication path issue includes at least one of a processing system mounting element issue, a circuit board trace issue, a connector issue, or a cable issue.

7. The system of claim 1 , wherein the communication path testing engine is configured to:

generate the expected impedance profile using an expected communication path in which no testing communication path issues exist.

8. An Information Handling System (IHS), comprising:

a processing system; and

a memory system that is coupled to the processing system and that includes instructions that, when executed by the processing system, cause the processing system to provide a communication path testing engine that is configured to:

generate at least one test signal and transmit the at least one test signal via a transmitter and through a testing communication path that is provided by a loop back subsystem between the transmitter and a receiver and that includes a plurality of different testing communication path portions;

receive, in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path that is provided by the loop back subsystem between the transmitter and the receiver and that includes a plurality of different testing communication path portions;

process the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testing communication path;

compare the testing impedance profile for the testing communication path to an expected impedance profile to determine whether a testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path; and

generate and transmit, in response to determining that the at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path, a testing communication path issue communication.

9. The IHS of claim 8 , wherein the at least one test signal is provided by at least one Time-Domain Reflectometer (TDR) step function and the at least one test signal result is provided by at least one TDR reflection.

10. The IHS of claim 8 , wherein the processing of the at least one test signal result to generate the testing impedance profile for the testing communication path includes performing a Fast Fourier Transform (FFT) on the at least one test signal result to generate a transfer function, and generating the testing impedance profile for the testing communication path based on the transfer function.

11. The IHS of claim 8 , wherein the plurality of different testing communication path portions included in the testing communication path provided between the transmitter and the receiver by the loop back subsystem includes at least one processing system mounting element portion, at least one circuit board trace portion, at least one connector portion, and at least one cable portion.

12. The IHS of claim 8 , wherein the testing communication path issue includes at least one of a processing system mounting element issue, a circuit board trace issue, a connector issue, or a cable issue.

13. The IHS of claim 7 , wherein the communication path testing engine is configured to:

generate the expected impedance profile using an expected communication path in which no testing communication path issues exist.

14. A method for testing high-speed signaling subsystem, comprising:

generating, by a communication path testing subsystem, at least one test signal;

transmitting, by the communication path testing subsystem, the at least one test signal via a transmitter and through a testing communication path that is provided by a loop back subsystem between the transmitter and a receiver and that includes a plurality of different testing communication path portions;

receiving, by the communication path testing subsystem in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path that is provided by the loop back subsystem between the transmitter and the receiver and that includes a plurality of different testing communication path portions;

processing, by the communication path testing subsystem, the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testing communication path;

comparing, by the communication path testing subsystem, the testing impedance profile for the testing communication path to an expected impedance profile to determine whether a testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path; and

generating and transmitting, by the communication path testing subsystem in response to determining that the at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path, a testing communication path issue communication.

15. The method of claim 14 , wherein the at least one test signal is provided by at least one step function and the at least one test signal result is provided by at least one reflection.

16. The method of claim 15 , wherein the at least one test signal is at least one Time-Domain Reflectometer (TDR) test signal and the at least one test signal result is at least one TDR reflection.

17. The method of claim 14 , wherein the processing of the at least one test signal result to generate the testing impedance profile for the testing communication path includes performing a Fast Fourier Transform (FFT) on the at least one test signal result to generate a transfer function, and generating the testing impedance profile for the testing communication path based on the transfer function.

18. The method of claim 14 , wherein the plurality of different testing communication path portions included in the testing communication path provided between the transmitter and the receiver by the loop back subsystem includes at least one processing system mounting element portion, at least one circuit board trace portion, at least one connector portion, and at least one cable portion.

19. The method of claim 14 , wherein the testing communication path issue includes at least one of a processing system mounting element issue, a circuit board trace issue, a connector issue, or a cable issue.

20. The method of claim 14 , further comprising:

generating, by the communication path testing subsystem, the expected impedance profile using an expected communication path in which no testing communication path issues exist.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (058014/0560) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0473 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057931/0392) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0382 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057758/0286) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 061654/0064 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 058014/0560 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057758/0286 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057931/0392 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2021
From: CHANDRA, UMESH; MUTNURY, BHYRAV
To: DELL PRODUCTS L.P.
Reel/Frame 056837/0509 →
Continuity (1)
Related Publication 20230018015A1 · Jan 19, 2023