System and method for device authentication using a baseboard management controller (BMC)

1. An Information Handling System (IHS), comprising:

a plurality of hardware devices; and

a Baseboard Management Controller (BMC) in communication with the plurality of hardware devices, the BMC comprising at least one memory having instructions stored thereon that, upon execution by at least one processor, cause the BMC to:

when one of the hardware devices is powered on, cause the one hardware device to be inhibited from functioning with the IHS;

perform an authentication procedure with the one hardware device;

after the one hardware device has been successfully authenticated, enable the one hardware device to function with the IHS; and

after the one hardware device has been unsuccessfully authenticated, inhibit the one hardware device from functioning with the IHS by communicating with a BMC software agent to disable a driver of the one hardware device from functioning on the IHS.

2. The IHS of claim 1 , wherein the instructions further cause the BMC to power on the one hardware device due to power being applied to the IHS.

3. The IHS of claim 1 , wherein the instructions further cause the BMC to power on the one hardware device due to being hot-plugged onto the IHS.

4. The IHS of claim 1 , wherein the IHS comprises a basic input output system (BIOS) configured to perform a power on self-test (POST) procedure, and wherein the instructions further cause the BMC to:

communicate with the bios of the IHS to delay completion of the POST until the one hardware device has been authenticated.

5. The IHS of claim 4 , wherein the IHS comprises a bus controller configured to control operations of a bus that communicatively couples the IHS to the one hardware device, and wherein the instructions further cause the BMC to cause the one hardware device to be inhibited from functioning with the IHS by communicating with the bus controller to disable the one hardware device from communicating through the bus.

6. The IHS of claim 5 , wherein the bus comprises a plurality of slots configured for coupling the one hardware device to the IHS, and wherein the instructions further cause the BMC to disable any empty slots of the bus.

7. The IHS of claim 4 , wherein the instructions further cause the BMC to perform the authentication procedure using a SPDM protocol.

8. A method comprising:

when one of a plurality of hardware devices of an information handling system (IHS) is powered on, causing, using instructions stored in at least one memory and executed by at least one processor, the one hardware device to be inhibited from functioning with the IHS;

performing, using the instructions, an authentication procedure with the one hardware device;

after the one hardware device has been successfully authenticated, enabling, using the instructions, the one hardware device to function with the IHS; and

after the one hardware device has been unsuccessfully authenticated, inhibiting, using the instructions, the one hardware device from functioning with the IHS by communicating with a BMC software agent to disable a driver of the one hardware device from functioning on the IHS.

9. The method of claim 8 , further comprising powering on the one hardware device by applying power to the IHS.

10. The method of claim 8 , further comprising powering on the one hardware device by hot-plugging the one hardware device onto the IHS.

11. The method of claim 8 , further comprising:

performing a power on self-test (POST) procedure; and

communicating with the bios of the IHS to delay completion of the post until the one hardware device has been authenticated.

12. The method of claim 11 , further comprising causing the one hardware device to be inhibited from functioning with the IHS by communicating with the bus controller to disable the one hardware device from communicating through the bus.

13. The method of claim 12 , further comprising disabling any empty slots of the bus.

14. The method of claim 11 , wherein the instructions perform the authentication procedure using a SPDM protocol.

15. A Baseboard Management Controller (BMC) comprising at least one memory having instructions stored thereon that, upon execution by at least one processor, cause the BMC to:

when one of a plurality of hardware devices of an information handling system (IHS) is powered on, cause the one hardware device to be inhibited from functioning with the IHS;

perform an authentication procedure with the one hardware device;

after the one hardware device has been successfully authenticated, enable the one hardware device to function with the IHS; and

after the one hardware device has been unsuccessfully authenticated, inhibit the one hardware device from functioning with the IHS by communicating with a BMC software agent to disable a driver of the one hardware device from functioning on the IHS.

16. The BMC of claim 15 , wherein the IHS comprises a bios configured to perform a power on self-test (POST) procedure, and wherein the instructions further cause the BMC to:

communicate with the bios of the IHS to delay completion of the post until the one hardware device has been authenticated.

17. The BMC of claim 16 , wherein the IHS comprises a bus controller configured to control operations of a bus that communicatively couples the IHS to the one hardware device, and wherein the instructions further cause the BMC to:

cause the one hardware device to be inhibited from functioning with the IHS by communicating with the bus controller to disable the one hardware device from communicating through the bus; and

disable any empty slots of the bus.