System and method for multi-node buffer transfer
A method, computer program product, and computing system for receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node. A target memory address within the remote persistent cache memory system may be sent from the local node via a remote procedure call (RPC). The data may be sent from the local node to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command.
1. A computer-implemented method, executed on a computing device, comprising:
receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node;
sending, from the local node, a target memory address within the remote persistent cache memory system via a remote procedure call (RPC);
sending, from the local node, the data to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command;
allocating, during initialization of the remote node, at least a portion of the remote persistent cache memory system for buffering data, thus defining one or more buffer portions;
sending, from the remote node to the local node, a memory address associated with a first buffer portion of the one or more buffer portions; and
generating a list of free buffer portions within the remote persistent cache memory system.
2. The computer-implemented method of claim 1 , wherein the remote persistent cache memory system includes a battery backup random access memory (RAM) system.
3. The computer-implemented method of claim 1 , further comprising:
determining the target memory address within the remote persistent cache memory system for buffering the data based upon, at least in part, the list of free buffer portions within the remote persistent cache memory system.
4. The computer-implemented method of claim 3 , further comprising:
remote persistent cache memory system via an RPC response; and
updating the list of free buffer portions within the remote persistent cache memory system based upon, at least in part, the updated target memory address.
5. The computer-implemented method of claim 1 , wherein the data to buffer on the remote persistent cache memory system of the remote node includes a cache status bitmap.
6. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node;
sending, from the local node, a target memory address within the remote persistent cache memory system via a remote procedure call (RPC);
sending, from the local node, the data to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command;
allocating, during initialization of the remote node, at least a portion of the remote persistent cache memory system for buffering data, thus defining one or more buffer portions;
sending, from the remote node to the local node, a memory address associated with a first buffer portion of the one or more buffer portions; and
generating a list of free buffer portions within the remote persistent cache memory system.
7. The computer program product of claim 6 , wherein the remote persistent cache memory system includes a battery backup random access memory (RAM) system.
8. The computer program product of claim 6 , wherein the operations further comprise:
determining the target memory address within the remote persistent cache memory system for buffering the data based upon, at least in part, the list of free buffer portions within the remote persistent cache memory system.
9. The computer program product of claim 8 , wherein the operations further comprise:
receiving, from the remote node, an updated target memory address within the remote persistent cache memory system via an RPC response; and
updating the list of free buffer portions within the remote persistent cache memory system based upon, at least in part, the updated target memory address.
10. The computer program product of claim 6 , wherein the data to buffer on the remote persistent cache memory system of the remote node includes a cache status bitmap.
11. A computing system comprising:
a memory; and
a processor configured to:
receive, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node;
send, from the local node, a target memory address within the remote persistent cache memory system via a remote procedure call (RPC);
send, from the local node, the data to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command;
allocate, during initialization of the remote node, at least a portion of the remote persistent cache memory system for buffering data, thus defining one or more buffer portions;
send, from the remote node to the local node, a memory address associated with a first buffer portion of the one or more buffer portions; and
generate a list of free buffer portions within the remote persistent cache memory system.
12. The computing system of claim 11 , wherein the remote persistent cache memory system includes a battery backup random access memory (RAM) system.
13. The computing system of claim 6 , wherein the processor is further configured to:
determine the target memory address within the remote persistent cache memory system for buffering the data based upon, at least in part, the list of free buffer portions within the remote persistent cache memory system.
14. The computing system of claim 13 , wherein the processor is further configured to:
receive, from the remote node, an updated target memory address within the remote persistent cache memory system via an RPC response; and
update the list of free buffer portions within the remote persistent cache memory system based upon, at least in part, the updated target memory address.