Granted Patent B2

US 12,376,481 · App. 17/382,425 · Granted Jul 29, 2025

Inventors: Jaebum Han (Yongin-si, KR); Younggil Park (Yongin-si, KR); Moonsung Kim (Yongin-si, KR); Jaisun Kyoung (Yongin-si, KR); Kihyun Kim (Yongin-si, KR); Sooim Jeong (Yongin-si, KR)

Assignee: Samsung Display Co., Ltd.

H10K77/10H10K59/124H10K59/12H10K59/1201

Abstract

Claims (23)

1. A display apparatus comprising:

a substrate including a first base layer, a second base layer arranged over the first base layer, and a first barrier layer disposed between the first base layer and the second base layer;

a first thin-film transistor arranged over the substrate and including a first semiconductor layer and a first gate electrode; and

a second thin-film transistor arranged over the substrate and including a second semiconductor layer and a second gate electrode,

wherein the first barrier layer includes a first sub-layer and a second sub-layer disposed on the first sub-layer, the first sub-layer including an inorganic material and the second sub-layer including amorphous silicon and crystallized silicon, and not including a conductive material,

wherein the first semiconductor layer includes a silicon-based semiconductor material, and the second semiconductor layer includes an oxide-based semiconductor material,

wherein the first thin-film transistor and the second thin-film transistor are disposed in a display area comprising a pixel circuit connected to an organic light-emitting diode,

wherein the second sub-layer includes a top surface having a surface roughness, which represents an unevenness in heights made by each of upper peaks and each of lower valleys in at least one part of the top surface, in a range from 0.02 nm to 0.5 nm, and

wherein the second sub-layer has a hydrogen concentration of from 4.0E+21 atom/cm 3 to 6.0E+21 atom/cm 3 , and the hydrogen concentration included in the second sub-layer controls the surface roughness of the top surface of the second sub-layer.

2. The display apparatus of claim 1 , wherein the crystallized silicon in the second sub-layer is from 2% to 25%.

3. The display apparatus of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are arranged on different layers.

4. The display apparatus of claim 1 , further comprising:

a gate insulating layer arranged between the first semiconductor layer and the first gate electrode; and

an interlayer insulating layer arranged between the first gate electrode and the second semiconductor layer.

5. The display apparatus of claim 4 , wherein the second semiconductor layer is arranged directly on the interlayer insulating layer.

6. The display apparatus of claim 1 , further comprising a bottom metal layer arranged between the substrate and the second semiconductor layer, the bottom metal layer being disposed on an area corresponding to the second semiconductor layer.

7. The display apparatus of claim 6 , wherein the first semiconductor layer does not overlap the bottom metal layer in a plan view.

8. The display apparatus of claim 1 , wherein the substrate further includes a second barrier layer disposed on the second base layer and including an inorganic material.

9. The display apparatus of claim 8 , further comprising a buffer layer arranged on the second barrier layer,

wherein the first semiconductor layer is arranged directly on the buffer layer.

10. The display apparatus of claim 1 , wherein the second sub-layer has an extinction coefficient of from 0.01 to 0.025.

11. The display apparatus of claim 1 , wherein the second sub-layer has a thickness of from 5 Å to 100 Å.

12. The display apparatus of claim 1 , wherein the first sub-layer has a thickness of from 4000 Å to 7000 Å.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (21)