IP Library Granted Patent US 11,979,976
Granted Patent B2
US 11,979,976 · App. 17/383,129 · Granted May 7, 2024

Methods of forming interconnect circuits

Inventors: Kevin Michael Coakley (Belmont, CA); Malcolm Parker Brown (Mountain View, CA); Dongao Yang (Redwood City, CA); Michael Lawrence Miller (San Mateo, CA); Paul Henry Lego (Woodside, CA)
Assignee: CelLink Corporation
H05K1/0201H01M50/519H05K1/118H05K3/007H05K3/0073H05K3/06H05K3/20H05K3/281H05K3/4623H05K3/046H05K3/064H05K3/44H05K3/445Y02E60/10
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Quick Facts
Patent No.
US 11,979,976
App. No.
17/383,129
Granted
May 7, 2024
Kind
B2
Abstract

Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

Claims (31)

1. A method of forming a flexible interconnect circuit, the method comprising:

laminating a substrate to a conductive layer, wherein:

the conductive layer is a metal foil having a constant thickness and comprises a first side and a second side, opposite of the first side, and

the substrate is laminated to the second side of the conductive layer;

patterning the conductive layer, while the conductive layer remains laminated to the substrate, wherein:

patterning the conductive layer comprises laser cutting by directing a laser beam to the conductive layer causing portions of the conductive layer to be removed,

patterning the conductive layer forms a first conductive portion and a second conductive portion of the conductive layer, at least partially separated from the first conductive portion by a pattern opening,

the pattern opening is defined by sidewalls of the first conductive portion and the second conductive portion, extending to the substrate,

the substrate extends across the pattern opening in the conductive layer such that the substrate maintains orientation of the first conductive portion relative to the second conductive portion during and after patterning,

the sidewalls are tapered such that the pattern opening is smaller at an interface with the substrate than away from the substrate, and

laminating a first insulator to the first side of the conductive layer such that the first insulator extends across the pattern opening and such that the pattern opening is larger at an additional interface with the first insulator than away from the first insulator.

2. The method of claim 1 , wherein the sidewalls have a smooth transition to the first side of the conductive layer.

3. The method of claim 1 , wherein the first side is substantially flat such that the constant thickness deviates less than 10%.

4. The method of claim 1 , wherein the pattern opening is defined by a first sidewall of the first conductive portion and a second sidewall of the second conductive portion such that each of the first sidewall and the second sidewall protrudes above the first side of the conductive layer forming a raised interface around the pattern opening.

5. The method of claim 1 , wherein:

patterning the conductive layer further forms a third conductive portion of the conductive layer, separated by a first pattern opening from the first conductive portion and also separated by a second pattern opening from the second conductive portion, and

patterning the conductive layer comprises removing the third conductive portion from the substrate thereby forming the pattern opening in place of the first pattern opening, the third conductive portion, and the second pattern opening.

6. The method of claim 5 , wherein removing the third conductive portion from the substrate is performed by peeling in a direction selected based on a shape of the pattern opening.

7. The method of claim 5 , wherein the third conductive portion of the conductive layer is removed from the substrate prior to laminating the first insulator to the first side of the conductive layer.

8. The method of claim 5 , wherein the third conductive portion of the conductive layer is removed from the substrate after laminating the first insulator to the first side of the conductive layer.

9. The method of claim 1 , wherein the first insulator comprises an opening prior to laminating the first insulator to the conductive layer.

10. The method of claim 9 , wherein the opening at least partially overlaps with the first conductive portion of the conductive layer such that the first side of the first conductive portion remains at least partially exposed after laminating to the first insulator.

11. The method of claim 1 , wherein patterning the conductive layer completely removes a portion of the conductive layer positioned between the first conductive portion and the second conductive portion.

12. The method of claim 1 , wherein the pattern opening has a variable width.

13. The method of claim 1 , wherein the substrate comprises an adhesive layer contacting the second side of the conductive layer, and wherein removing the substrate further comprises deactivating at least a portion of the adhesive layer.

14. The method of claim 1 , further comprising removing the substrate from the conductive layer, wherein the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion after the substrate is removed.

15. The method of claim 14 , further comprising:

laminating a second device stack comprising a second substrate, a third conductive portion, and an insulator adhesive to the first insulator of a first device stack further comprising the first conductive portion such that the third conductive portion overlaps with the first conductive portion; and

electrically connecting the third conductive portion with the first conductive portion.

16. The method of claim 15 , wherein electrically connecting the third conductive portion with the first conductive portion comprises pushing either the third conductive portion of the first conductive portion into a gap between the third conductive portion and the first conductive portion and welding, soldering, or crimping the third conductive portion and the first conductive portion.

17. The method of claim 1 , wherein directing the laser beam to the conductive layer further causes the portions of the conductive layer to burn and vaporize away forming the pattern opening.

Assignments (2)
NOTICE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Apr 18, 2024
From: CELLINK CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 067166/0404 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2021
From: COAKLEY, KEVIN MICHAEL; BROWN, MALCOLM PARKER; YANG, DONGAO; MILLER, MICHAEL LAWRENCE; LEGO, PAUL HENRY
To: CELLINK CORPORATION
Reel/Frame 057329/0839 →
Continuity (3)
Continuation 16034899 · Jul 13, 2018
Provisional Application 62531995 · Jul 13, 2017
Related Publication 20210352798A1 · Nov 11, 2021
Cited By (10)
US 12,300,854 US 12,471,245 US 12,510,598 US 12,525,671 US 12,542,330 US 12,567,611 US 12,573,694 US 12,589,642 US 12,604,404 US 12,646,787