Granted Patent B2

US 11,586,569 · App. 17/383,604 · Granted Feb 21, 2023

Inventors: Leonid Ravich (Raanana, IL); Eldad Zinger (Raanana, IL); Amit Engel (Tel Aviv, IL)

Assignee: EMC IP Holding Company, LLC

G06F13/24G06F13/102

Abstract

Claims (50)

1. A computer-implemented method, executed on a computing device, comprising:

assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores;

assigning a second set of interrupts for processing by a second set of CPU cores;

processing the first set of interrupts using the first set of CPU cores;

converting the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations; and

processing the set of converted polling operations using the second set of CPU cores.

2. The computer-implemented method of claim 1 , wherein converting the second set of interrupts to a set of polling operations includes:

preventing the second set of interrupts from being processed as interrupts; and

storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

3. The computer-implemented method of claim 2 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

4. The computer-implemented method of claim 1 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

5. The computer-implemented method of claim 4 , wherein the first set of interrupts include one or more IO command interrupts.

6. The computer-implemented method of claim 5 , further comprising:

determining, using the one or more IO command interrupts, whether an IO command interrupt is associated with a read command or a write command;

in response to determining that the IO command interrupt is associated with a read command, converting the read command interrupt to a polling operation; and

in response to determining that the IO command interrupt is associated with a write command, processing the write command interrupt using the first set of CPU cores.

7. The computer-implemented method of claim 4 , wherein the second set of interrupts include at least one of:

one or more backend submission command interrupts; and

one or more transaction completion interrupts.

8. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores;

assigning a second set of interrupts for processing by a second set of CPU cores;

processing the first set of interrupts using the first set of CPU cores;

converting the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations; and

processing the set of converted polling operations using the second set of CPU cores.

9. The computer program product of claim 8 , wherein converting the second set of interrupts to a set of polling operations includes:

preventing the second set of interrupts from being processed as interrupts; and

storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

10. The computer program product of claim 9 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

11. The computer program product of claim 8 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

12. The computer program product of claim 11 , wherein the first set of interrupts include one or more IO command interrupts.

13. The computer program product of claim 12 , wherein the operations further comprise:

determining, using the one or more IO command interrupts, whether an IO command interrupt is associated with a read command or a write command;

in response to determining that the IO command interrupt is associated with a read command, converting the read command interrupt to a polling operation; and

in response to determining that the IO command interrupt is associated with a write command, processing the write command interrupt using the first set of CPU cores.

14. The computer program product of claim 11 , wherein the second set of interrupts include at least one of:

one or more backend submission command interrupts; and

one or more transaction completion interrupts.

15. A computing system comprising:

a memory; and

a processor configured to assign a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores, wherein the processor is further configured to assign a second set of interrupts for processing by a second set of CPU cores, wherein the processor is further configured to process the first set of interrupts using the first set of CPU cores, wherein the processor is further configured to convert the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations, and wherein the processor is further configured to process the set of converted polling operations using the second set of CPU cores.

16. The computing system of claim 15 , wherein converting the second set of interrupts to a set of polling operations includes:

preventing the second set of interrupts from being processed as interrupts; and

storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

17. The computing system of claim 16 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

18. The computing system of claim 15 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

19. The computing system of claim 18 , wherein the first set of interrupts include one or more IO command interrupts.

20. The computing system of claim 18 , wherein the second set of interrupts include at least one of:

one or more backend submission command interrupts; and

one or more transaction completion interrupts.

Assignments (8)

Continuity (1)