IP Library Granted Patent US 12,230,988
Granted Patent B2
US 12,230,988 · App. 17/383,865 · Granted Feb 18, 2025

Constant current charging capacitor test

Inventors: Adrian Mocanu (Langley, CA); Zeljko Zupanc (Vancouver, CA); Derrick Wilson (North Vancouver, CA); Andrew Morning-Smith (Vancouver, CA)
Assignee: Intel Corporation
H02J7/005G11C5/10G11C5/14G11C5/141G11C5/145H02J7/007182H02J7/345
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Quick Facts
Patent No.
US 12,230,988
App. No.
17/383,865
Granted
Feb 18, 2025
Kind
B2
Abstract

Systems, apparatuses and methods may provide for technology that applies a constant current to a capacitor, wherein the constant current causes a linear voltage increase in the capacitor, and determines a capacitance based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

Claims (33)

1. A solid state drive (SSD) comprising:

a non-volatile memory (NVM); and

a power management subsystem coupled to the NVM, the power management subsystem comprising:

a capacitor,

a charge circuit coupled to the capacitor via a first switch, wherein the charge circuit is to apply a constant current to the capacitor, and wherein the constant current causes a linear voltage increase in the capacitor,

a boost stage coupled to the capacitor via a second switch, wherein the boost stage is separate from the charge circuit and is to charge the capacitor to a voltage that is greater than an input voltage, and

a measurement circuit coupled to the capacitor, wherein the measurement circuit is to determine a capacitance of the capacitor based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

2. The SSD of claim 1 , wherein the measurement circuit is to conduct a health check of the capacitor based on the capacitance before completion of a boost phase with respect to the capacitor.

3. The SSD of claim 1 , wherein the charge circuit is to remove the constant current from the capacitor, wherein removal of the constant current causes an instantaneous voltage shift at the capacitor, and wherein the measurement circuit is to determine an equivalent series resistance of the capacitor based on the instantaneous voltage shift.

4. The SSD of claim 3 , wherein the constant current is removed from the capacitor when the capacitor reaches an input voltage.

5. The SSD of claim 1 , wherein the constant current is applied during a boot of the SSD.

6. A power management subsystem comprising:

a capacitor;

a charge circuit coupled to the capacitor via a first switch, wherein the charge circuit is to apply a constant current to the capacitor, and wherein the constant current causes a linear voltage increase in the capacitor;

a boost stage coupled to the capacitor via a second switch, wherein the boost stage is separate from the charge circuit and is to charge the capacitor to a voltage that is greater than an input voltage, and

a measurement circuit coupled to the capacitor, wherein the measurement circuit is to determine a capacitance of the capacitor based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

7. The power management subsystem of claim 6 , wherein the measurement circuit is to conduct a health check of the capacitor based on the capacitance before completion of a boost phase with respect to the capacitor.

8. The power management subsystem of claim 6 , wherein the charge circuit is to remove the constant current from the capacitor, wherein removal of the constant current causes an instantaneous voltage shift at the capacitor, and wherein the measurement circuit is to determine an equivalent series resistance of the capacitor based on the instantaneous voltage shift.

9. The power management subsystem of claim 8 , wherein the constant current is removed from the capacitor when the capacitor reaches an input voltage.

10. The power management subsystem of claim 6 , wherein the constant current is applied during a boot of a solid state drive containing the power management subsystem.

11. The power management subsystem of claim 6 , wherein the capacitor is a solid state drive holdup capacitor.

12. A method comprising:

applying, using a charge circuit coupled to a capacitor via a first switch, a constant current to the capacitor, wherein the constant current causes a linear voltage increase in the capacitor;

charging, using a boost stage coupled to the capacitor via a second switch, the capacitor to a voltage that is greater than an input voltage, wherein the boost stage is separate from the charge circuit, and

determining a capacitance of the capacitor based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

13. The method of claim 12 , further including conducting a health check of the capacitor based on the capacitance before completion of a boost phase with respect to the capacitor.

14. The method of claim 12 , further including:

removing the constant current from the capacitor, wherein removal of the constant current causes an instantaneous voltage shift in the capacitor; and

determining an equivalent series resistance of the capacitor based on the instantaneous voltage shift.

15. The method of claim 14 , wherein the constant current is removed from the capacitor when the capacitor reaches an input voltage.

16. The method of claim 14 , further including charging the capacitor to a voltage that is greater than an input voltage.

17. The method of claim 12 , wherein the constant current is applied during a boot of a solid state drive.

18. The method of claim 12 , wherein the capacitor is a solid state drive holdup capacitor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072914/0491 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: MOCANU, ADRIAN; ZUPANC, ZELJKO; WILSON, DERRICK; MORNING-SMITH, ANDREW
To: INTEL CORPORATION
Reel/Frame 056973/0421 →
Continuity (1)
Related Publication 20210351595A1 · Nov 11, 2021
References Cited (3)
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