IP Library Granted Patent US 11,490,504
Granted Patent B2
US 11,490,504 · App. 17/384,675 · Granted Nov 1, 2022

High-speed trace breakout methods and systems

Inventor: Umesh Chandra (Santa Cruz, CA)
Assignee: DELL PRODUCTS L.P.
H05K1/0228H05K1/116H05K2201/09509
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Quick Facts
Patent No.
US 11,490,504
App. No.
17/384,675
Granted
Nov 1, 2022
Kind
B2
Abstract

A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

Claims (26)

1. A circuit comprising:

a first pin leg positioned in a direction towards a first edge of a printed circuit board (PCB) and using a first via to couple a first surface of the PCB to a first signal path that beaks out in the direction towards the first edge; and

a second pin leg positioned in a direction towards a second edge of the PCB and being disposed on a second surface of the PCB opposite to the first surface of the PCB, the second pin leg using a second via to couple the second surface of the PCB to a second signal path that breaks out in the direction towards the second edge.

2. The circuit of claim 1 , further comprising a signal via that couples the first surface of the PCB and the first signal path.

3. The circuit of claim 2 , wherein the signal via is a blind via.

4. The circuit of claim 1 , wherein the first signal path is arranged in a stripline configuration and is at least partially formed between a first ground path and a second ground path.

5. The circuit of claim 4 , wherein the first ground path is disposed adjacent to the first surface of the PCB.

6. The circuit of claim 4 , wherein the first ground path and at least a portion of the first surface of the PCB form a micro strip.

7. The circuit of claim 4 , further comprising a ground via that couples the first surface of the PCB to the first ground path, the first signal path, and the second ground path to reduce unwanted signal emissions.

8. The circuit of claim 7 , wherein the ground via is a plated through hole that extends from the first surface of the PCB to the second surface of the PCB.

9. The circuit of claim 7 , wherein a portion of the ground via that extends from the first surface of the PCB to the first signal path serves as a return path for a signal via that couples the first surface of the PCB with the first signal path.

10. A circuit comprising:

a pin leg positioned in a direction towards an edge of a printed circuit board (PCB) and using a first via in the PCB to couple a first surface of the PCB to a first signal path in the PCB, first signal path being at least partially formed between a first ground path and a second ground path and breaking out in the direction towards the edge; and

a ground via that couples the first surface of the PCB to the first ground path, the first signal path, and the second ground path to reduce unwanted signal emissions.

11. The circuit of claim 10 , wherein a portion of the ground via that extends from the first surface to the first signal path serves as a return path for a signal via that couples the first surface with the first signal path.

12. The circuit of claim 10 , wherein the ground via is a plated through hole that extends from the first surface of the PCB to the second surface of the PCB.

13. The circuit of claim 10 , further comprising a blind via that couples the first surface of the PCB with the first signal path.

14. The circuit of claim 10 , wherein the first ground path and at least a portion of the first surface of the PCB form a micro strip.

15. A method for reducing or eliminating unwanted resonant stub effects while controlling impedance of a signal breakout on a printed circuit board (PCB), the method comprising:

applying a first voltage to a first signal path coupled to a first connector pin having a first connector pin leg that is disposed on a first surface of the PCB, is positioned in a direction towards a first edge of the PCB, and uses a first via to couple the first surface of the PCB to the first signal path that breaks out in the direction towards the first edge; and

applying a second voltage to a second signal path coupled to a second connector pin having a second connector pin leg that is disposed on a second surface of the PCB, is positioned in a direction towards a second edge of the PCB, and uses a second via to couple the second surface of the PCB to the second signal path that breaks out in the direction towards the second edge.

16. The method of claim 15 , further comprising a blind via that couples the first surface of the PCB with the first signal path.

17. The method of claim 15 , wherein the first signal path is arranged in a stripline configuration, the first signal path being at least partially formed between a first ground path and a second ground path.

18. The method of claim 17 , further comprising a ground via that couples the first surface of the PCB to the first ground path, the first signal path, and the second ground path to reduce unwanted signal emissions, the ground via not being a blind via.

19. The method of claim 18 , wherein a portion of the ground via that extends from the first surface of the PCB to a second layer serves as a return path for a signal via that couples the first surface of the PCB with the first signal path.

20. The method of claim 18 , wherein the first ground path and at least a portion of the first surface of the PCB form a microstrip.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (058014/0560) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0473 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057758/0286) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 061654/0064 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057931/0392) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0382 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 058014/0560 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057758/0286 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057931/0392 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
Continuity (2)
Continuation 17061483 · Oct 1, 2020
Related Publication 20220110207A1 · Apr 7, 2022