Encapsulated semiconductor package
A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.
1. An integrated circuit package comprising:
a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising:
a first conductive layer comprising a first trace;
a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side;
a second conductive layer comprising a second trace; and
a third conductive layer comprising a conductive via;
an integrated circuit die comprising:
a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and
a die pad at the second die side,
where:
the first die side faces away from the SRS;
the second die side faces the SRS; and
the second die side is coupled to the first SRS side; and
an encapsulating structure that laterally surrounds at least the integrated circuit die and the first dielectric layer of the SRS, and directly contacts the lateral DL side.
2. The integrated circuit package of claim 1 , wherein the encapsulating structure vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
3. The integrated circuit package of claim 1 , wherein:
the encapsulating structure directly contacts the lateral die side;
the encapsulating structure directly contacts the second die side; and
the encapsulating structure directly contacts the first SRS side.
4. The integrated circuit package of claim 1 , wherein the encapsulating structure comprises an epoxy molding compound.
5. The integrated circuit package of claim 1 , wherein the encapsulating structure comprises:
a first encapsulating part that laterally surrounds the integrated circuit die and directly contacts the lateral die side; and
a second encapsulating part that laterally surrounds the first dielectric layer of the SRS and directly contacts the lateral DL side.
6. The integrated circuit package of claim 1 , wherein the signal redistribution structure (SRS) comprises a ball pad at the second SRS side.
7. The integrated circuit package of claim 1 , wherein the signal redistribution structure (SRS) comprises:
a first ball pad at the second SRS side and positioned within a footprint of the integrated circuit die; and
a second ball pad at the second SRS side and positioned outside of the footprint of the integrated circuit die.
8. The integrated circuit package of claim 1 , wherein the encapsulating structure comprises a planar lateral side surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side.
9. An integrated circuit package comprising:
a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising:
a first conductive layer comprising a first trace;
a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side;
a second conductive layer comprising a second trace; and
a third conductive layer comprising a plurality of pads;
an integrated circuit die comprising:
a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and
a die pad at the second die side,
where the second die side faces and is coupled to the first SRS side; and
an encapsulating layer comprising a first encapsulating layer side that faces a same direction as the first die side, a second encapsulating layer side that faces a same direction as the second die side, and a lateral encapsulating layer side that extends between the first encapsulating layer side and the second encapsulating layer side, where:
the encapsulating layer directly contacts the lateral DL side;
each of the pads of the third conductive layer comprises an exposed pad side that faces a same direction as the second encapsulating layer side and is exposed from the encapsulating layer at the second SRS side; and
the encapsulating layer laterally surrounds the pads of the third conductive layer.
10. The integrated circuit package of claim 9 , wherein a portion of the second encapsulating layer side is substantially at a same vertical level as the exposed pad sides of the pads of the third conductive layer.
11. The integrated circuit package of claim 9 , wherein the encapsulating layer vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
12. The integrated circuit package of claim 9 , wherein the encapsulating layer comprises an epoxy molding compound.
13. The integrated circuit package of claim 9 , wherein the encapsulating layer directly contacts each of the pads of the third conductive layer.
14. The integrated circuit package of claim 9 , wherein:
a first pad of the plurality of pads of the third conductive layer is positioned at the second SRS side and within a footprint of the integrated circuit die; and
a second pad of the plurality of pads of the third conductive layer is positioned at the second SRS side and outside of the footprint of the integrated circuit die.
15. The integrated circuit package of claim 9 , wherein the lateral encapsulating layer side comprises a planar surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side.
16. An integrated circuit package comprising:
a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising:
a first conductive layer comprising a first trace;
a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side;
a second conductive layer comprising a second trace; and
a third conductive layer comprising a conductive via;
an integrated circuit die comprising:
a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and
a die pad at the second die side,
where the second die side faces and is coupled to the first SRS side; and
an encapsulating layer comprising a first encapsulating layer side that faces a same direction as the first die side, a second encapsulating layer side that faces a same direction as the second die side, and a lateral encapsulating layer side that extends between the first encapsulating layer side and the second encapsulating layer side,
where a portion of the second encapsulating layer side around a perimeter of the second SRS side is exposed at an exterior of the integrated circuit package.
17. The integrated circuit package of claim 16 , wherein a portion of the second encapsulating layer side is substantially at a same vertical level as the second SRS side.
18. The integrated circuit package of claim 16 , wherein the encapsulating layer vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
19. The integrated circuit package of claim 16 , wherein the encapsulating layer comprises an epoxy molding compound.
20. The integrated circuit package of claim 16 , wherein the lateral encapsulating layer side comprises a planar surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side.