Trust verification system and method for a baseboard management controller (BMC)
An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes instructions for executing a bootloader to verify an integrity of a first firmware stack, and boot the first firmware stack on a first processor. Once booted, the first firmware stack verifies the integrity of a first code segment on a second processor that is also used to execute a custom BMC firmware stack. The first code segment is executed to verify the integrity of one or more vendor supplied code segments executed on the second processor.
1. An information handling system (IHS) comprising:
a plurality of hardware devices; and
a baseboard management controller (BMC) in communication with the plurality of hardware devices, the BMC comprising a plurality of processors and one or more memory units including instructions that, upon execution by the processors, are executed to:
execute a bootloader to verify an integrity of a first firmware stack, and boot the first firmware stack on a first of the processors; and
execute the first firmware stack to verify the integrity of a first code segment,
wherein the first code segment is executed on a second of the one or more processors,
wherein the first code segment is associated with an online assistance service managed by a vendor of the BMC, the online assistance service is executed to monitor the operations of the custom BMC firmware stack;
wherein the second processor is configured to execute a custom BMC firmware stack, and
wherein the first code segment is executed to verify the integrity of one or more vendor supplied code segments executed on the second processor.
2. The IHS of claim 1 , wherein the first processor comprises a coprocessor and the second processor comprises a baseboard processor, the coprocessor and baseboard processor configured in a system on chip (SoC) device.
3. The IHS of claim 2 , wherein the first firmware stack is executed on the first processor to verify the integrity of the first code segment using a hash algorithm engine configured on the SoC device.
4. The IHS of claim 1 , wherein the first code segment comprises a kernel driver stored in a kernel space of the second processor.
5. The IHS of claim 1 , wherein the first firmware stack, first code segment, and bootloader comprise a trusted execution environment that is inhibited from access by the custom BMC firmware stack.
6. The IHS of claim 1 , wherein the vendor supplied code segments comprise applications (APPs) that are configured to be downloaded from the online assistance service.
7. The IHS of claim 1 , wherein the first code segment is executed on the second processor to verify the integrity of the vendor supplied code segments each time they are started on the BMC.
8. The IHS of claim 1 , wherein the first firmware stack is executed on the first processor to verify the integrity of the first code segment at ongoing intervals.
9. The IHS of claim 1 , wherein the first firmware stack is executed on the first processor to send an event notification message to an administrative computer associated with the IHS when the verification fails.
10. A trust verification method comprising:
executing, using instructions stored in at least one memory and executed by a plurality of processors, a bootloader to verify an integrity of a first firmware stack on a baseboard management controller (BMC), and boot the first firmware stack on a first of the processors; and
executing, using the instructions, the first firmware stack to verify the integrity of a first code segment,
wherein the first code segment is executed on a second of the processors,
wherein the first code segment is associated with an online assistance service managed by a vendor of the BMC, the online assistance service is executed to monitor the operations of the custom BMC firmware stack;
wherein the second processor is configured to execute a custom BMC firmware stack, and
wherein the first code segment is executed to verify the integrity of one or more vendor supplied code segments executed on the second processor.
11. The trust verification method of claim 10 , further comprising executing, by the first firmware stack, to verify the integrity of the first code segment using a hash algorithm engine configured on the SoC device.
12. The trust verification method of claim 10 , further comprising inhibiting access to the first firmware stack, the first code segment, and the bootloader from access by the custom BMC firmware stack, the first firmware stack, the first code segment, and the bootloader comprising a trusted execution environment.
13. The trust verification method of claim 10 , further comprising downloading the vendor supplied code segments from the online assistance service, wherein the vendor supplied code segments comprise applications (APPs).
14. The trust verification method of claim 10 , further comprising executing the first code segment to verify the integrity of the vendor supplied code segments each time they are started on the BMC.
15. The trust verification method of claim 10 , further comprising executing the first firmware stack on the first processor to verify the integrity of the first code segment at ongoing intervals.
16. The trust verification method of claim 10 , further comprising executing the first firmware stack on the first processor to send an event notification message to an administrative computer associated with the IHS when the verification fails.
17. A baseboard management controller (BMC) comprising:
a baseboard management controller (BMC) in communication with a plurality of hardware devices of an information handling system (IHS), the BMC comprising a plurality of processors and one or more memory units including instructions that, upon execution by the processors, are executed to:
execute a bootloader to verify an integrity of a first firmware stack, and boot the first firmware stack on a first of the processors; and
execute the first firmware stack to verify the integrity of a first code segment,
wherein the first code segment is executed on a second of the processors,
wherein the first code segment is associated with an online assistance service managed by a vendor of the BMC, the online assistance service is executed to monitor the operations of the custom BMC firmware stack;
wherein the second processor is configured to execute a custom BMC firmware stack, and
wherein the first code segment is executed to verify the integrity of one or more vendor supplied code segments executed on the second processor.
18. The BMC of claim 17 , wherein the first code segment comprises a kernel driver stored in a kernel space of the second processor, wherein the first code segment is executed on the second processor to verify the integrity of the vendor supplied code segments each time they are started on the BMC, and wherein the first firmware stack is executed on the first processor to verify the integrity of the first code segment at ongoing intervals.