Three-dimensional memory device structures and methods
A method of fabricating a semiconductor device includes forming a first stack of semiconductor layers on a substrate. The first stack of semiconductor layers includes alternating first and second semiconductor strips. The first and second semiconductor strips includes first and second semiconductor materials, respectively. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first stack of semiconductor layers. The method further includes depositing a dielectric structure layer and a first conductive fill material in the voids to surround the second semiconductor strips. Further, the method includes removing the second semiconductor strips to form a second set of voids, and depositing a third semiconductor material in the second sets of voids.
1. A method of fabricating a semiconductor device, comprising:
forming first and second stacked structures in first and second device regions on a substrate, respectively, each of the first and second stacked structures comprising a stack of alternating first and second semiconductor strips, the first and second semiconductor strips comprising first and second semiconductor materials, respectively;
removing the first semiconductor strips to form first voids between the second semiconductor strips in both the first and the second stacked structures;
depositing a first dielectric structure layer and a second dielectric structure layer in the first voids to surround the second semiconductor strips in the first and second stacked structures, respectively;
depositing a first conductive fill material in the first voids to surround the first dielectric structure layer and the second dielectric structure layer, respectively; and
in the first device region, removing the second semiconductor strips to form second voids between portions of the first dielectric structure layer, and depositing a third semiconductor material in the second voids between portions of the first dielectric structure layer;
whereby the third semiconductor material is configured to form channel, source, and drain regions of a one-transistor ferroelectric random access memory (1T-FeRAM) in the first device region, the first conductive fill material is configured to form a gate electrode for the 1T-FeRAM, and the first conductive fill material is configured to form a gate electrode for a gate-all-around (GAA) transistor in the second device region.
2. The method of claim 1 , wherein removing the first semiconductor strips to form the first voids further comprises:
removing portions of the second semiconductor strips to form recessed regions;
depositing a dielectric material in the recessed regions; and
removing the first semiconductor strips, using the dielectric material in the recessed regions as a mask, to form the first voids between the second semiconductor strips in the first stacked structure.
3. The method of claim 1 , wherein depositing the first dielectric structure layer to surround the second semiconductor strips further comprises:
depositing a first ferroelectric material layer to surround the second semiconductor strips.
4. The method of claim 1 , wherein the first conductive fill material comprises titanium nitride (TiN) and tungsten (W).
5. The method of claim 1 , wherein the third semiconductor material comprises indium gallium zinc oxide (IGZO).
6. The method of claim 1 , wherein:
the first dielectric structure layer comprises hafnium zirconium oxide (HfZrO); and
the second dielectric structure layer comprises hafnium oxide (HfO 2 ).
7. A method of fabricating a semiconductor device, comprising:
forming a first stack of semiconductor layers in a first device region on a substrate, the first stack of semiconductor layers comprising alternating first and second semiconductor strips, the first and second semiconductor strips comprising first and second semiconductor materials, respectively;
removing the first semiconductor strips to form first voids between the second semiconductor strips in the first stack of semiconductor layers;
depositing a first dielectric structure layer in the first voids to surround the second semiconductor strips;
depositing a first conductive fill material in the first voids to surround the first dielectric structure layer and the second semiconductor strips;
removing the second semiconductor strips to form second voids between portions of the first dielectric structure layer; and
depositing a third semiconductor material in the second voids.
8. The method of claim 7 , wherein removing the first semiconductor strips to form the first voids further comprises:
removing portions of the second semiconductor strips to form recessed regions;
depositing a dielectric material in the recessed regions; and
removing the first semiconductor strips, using the dielectric material in the recessed regions as a mask, to form the first voids between the second semiconductor strips in the first stack of semiconductor layers.
9. The method of claim 7 , wherein depositing the first dielectric structure layer to surround the second semiconductor strips further comprises:
depositing a first ferroelectric material layer to surround the second semiconductor strips.
10. The method of claim 7 , wherein the first conductive fill material comprises titanium nitride (TiN) and tungsten (W).
11. The method of claim 7 , wherein the third semiconductor material comprises indium gallium zinc oxide (IGZO).
12. The method of claim 7 , wherein the first dielectric structure layer comprises hafnium zirconium oxide (HfZrO).
13. The method of claim 7 further comprising:
forming a second stack of semiconductor layers in a second device region on the substrate, the second stack of semiconductor layers comprising alternating third and fourth semiconductor strips;
removing the third semiconductor strips to form voids between the fourth semiconductor strips in the second stack of semiconductor layers;
depositing a second dielectric structure layer to surround the fourth semiconductor strips; and
depositing the first conductive fill material to surround the second dielectric structure layer and the second semiconductor strips,
whereby the first conductive fill material is configured to form a gate electrode of a transistor device in the second device region.
14. A semiconductor device, comprising:
an integral semiconductor structure in a first device region of a substrate, the integral semiconductor structure including a same semiconductor material forming first and second portions connected by stacked strips of the same semiconductor material, the stacked strips being separated from one another;
a conductive electrode layer wrapped around the stacked strips of the integral semiconductor structure; and
a first dielectric structure layer separating the stacked strips from the conductive electrode layer.
15. The semiconductor device of claim 14 , wherein:
the same semiconductor material is disposed in interconnected voids in the semiconductor device, the interconnected voids including stacked voids connecting a void in the first portion and a void in the second portion.
16. The semiconductor device of claim 14 , further comprising:
stacked semiconductor strips disposed in a second device region of the substrate and separated from one another;
a second dielectric structure layer wrapped around the stacked semiconductor strips; and
the conductive electrode layer wrapped around the second dielectric structure layer and the stacked semiconductor strips.
17. The semiconductor device of claim 16 , wherein:
the second dielectric structure layer comprises hafnium oxide (HfO 2 ); and
in the second device region, the stacked semiconductor strips are configured to form channels of a transistor, and the conductive electrode layer is configured to form a gate of a transistor.
18. The semiconductor device of claim 14 , wherein:
the first dielectric structure layer comprises hafnium zirconium oxide (HfZrO); and
in the first device region, the integral semiconductor structure, the first dielectric structure layer, and the conductive electrode layer are configured to form an indium gallium zinc oxide ferroelectric random access memory (IGZO FeRAM) cell.
19. The semiconductor device of claim 14 , wherein:
in the first device region, the stacked semiconductor strips are configured to form channels of a transistor, and the first and second portions are configured as source and drain regions, respectively.
20. A semiconductor device, comprising:
an integral semiconductor structure in a first device region of a substrate, the integral semiconductor structure including a same semiconductor material forming first and second portions connected by stacked strips of the same semiconductor material, the stacked strips being separated from one another;
a conductive electrode layer wrapped around the stacked strips of the integral semiconductor structure; and
a first dielectric structure layer separating the stacked strips from the conductive electrode layer,
wherein the same semiconductor material comprises indium gallium zinc oxide (IGZO).