System and method for generation of configuration descriptors for a chipset
A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.
1. A chipset configuration descriptor generation system, comprising:
a chipset including a plurality of chipset ports;
a plurality of endpoint devices;
a respective platform connector connected to each of the plurality of chipset ports to provide a plurality of chipset port/platform connector combinations that each provide a link to at least one of the plurality of endpoint devices; and
a chipset port configuration generation subsystem that is coupled to the chipset and that is configured, during first initialization operations, to:
determine a respective first port configuration for each of the plurality of chipset ports based on 1) a plurality of first desired interface properties for the link provided to the at least one of the plurality of endpoint devices connected to the chipset port/platform connector combination that includes that chipset port, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port;
generate a first chipset configuration descriptor using the respective first port configurations; and
configure the plurality of chipset ports using the first chipset port configuration descriptor.
2. The system of claim 1 , wherein the chipset port configuration generation subsystem is provided by a Basic Input Output System (BIOS).
3. The system of claim 1 , wherein the determining the respective first port configuration for each of the plurality of chipset ports includes:
determining a number of the plurality of endpoint devices connected via the respective platform connector to that chipset port; and
bifurcating that chipset port based on the number of the plurality of endpoint devices connected via the respective platform connector to that chipset port.
4. The system of claim 1 , wherein the respective first port configuration for each of the plurality of chipset ports is selected from chipset capability information that is included in the chipset port configuration generation subsystem and that identifies the capabilities of each of the plurality of chipset ports.
5. The system of claim 1 , wherein the respective first port configuration for each of the plurality of chipset ports includes at least one of a hotplug configuration, a power configuration, a lane configuration, and a bifurcation configuration.
6. The system of claim 1 , wherein the chipset port configuration generation subsystem is configured, during second initialization operations, to:
determine a respective second port configuration for each of the plurality of chipset ports based on 1) a plurality of second desired interface properties for the link provided to the at least one of the plurality of endpoint devices connected to the chipset port/platform connector combination that includes that chipset port, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port, wherein at least one of the respective second port configurations is different than at least one of the respective first port configurations;
generate a second chipset configuration descriptor using the respective second port configurations, wherein the second chipset configuration descriptor is different than the first chipset configuration descriptor; and
configure the plurality of chipset ports using the second chipset port configuration descriptor.
7. An Information Handling System (IHS), comprising:
a processing system; and
a memory system that includes instructions that, when executed by the processing system, cause the processing system to provide a chipset port configuration generation engine that is configured, during first initialization operations, to:
determine a respective first port configuration for each of a plurality of chipset ports on a chipset that is coupled to the processing system based on 1) a plurality of first desired interface properties for a link provided to at least one of a plurality of endpoint devices connected to a chipset port/platform connector combination that includes that chipset port and a respective platform connector, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port;
generate a first chipset configuration descriptor using the respective first port configurations; and
configure the plurality of chipset ports using the first chipset port configuration descriptor.
8. The IHS of claim 7 , wherein the chipset port configuration generation engine is provided by a Basic Input Output System (BIOS).
9. The IHS of claim 7 , wherein the determining the respective first port configuration for each of the plurality of chipset ports includes:
determining a number of the plurality of endpoint devices connected via the respective platform connector to that chipset port; and
bifurcating that chipset port based on the number of the plurality of endpoint devices connected via the respective platform connector to that chipset port.
10. The IHS of claim 7 , wherein the respective first port configuration for each of the plurality of chipset ports is selected from chipset capability information that is included in the chipset port configuration generation engine and that identifies the capabilities of each of the plurality of chipset ports.
11. The IHS of claim 7 , wherein the respective first port configuration for each of the plurality of chipset ports includes at least one of a hotplug configuration, a power configuration, a lane configuration, and a bifurcation configuration.
12. The IHS of claim 7 , wherein the chipset port configuration generation engine is configured, during second initialization operations, to:
determine a respective second port configuration for each of the plurality of chipset ports based on 1) a plurality of second desired interface properties for the link provided to the at least one of the plurality of endpoint devices provided to the at least one of the plurality of endpoint devices connected to the chip set port/platform connector combination that includes that chipset port, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port, wherein at least one of the respective second port configurations is different than at least one of the respective first port configurations;
generate a second chipset configuration descriptor using the respective second port configurations, wherein the second chipset configuration descriptor is different than the first chipset configuration descriptor; and
configure the plurality of chipset ports using the second chipset port configuration descriptor.
13. The IHS of claim 12 , wherein the at least one of the respective second port configurations is different than the at least one of the respective first port configurations based on a change in the connection of the at least one of the plurality of endpoint devices to at least one of the chipset ports/platform connector combinations.
14. A method for generating a chipset configuration descriptor, comprising:
determining, by a chipset port configuration generation subsystem during first initialization operations, a respective first port configuration for each of a plurality of chipset ports on a chipset based on 1) a plurality of first desired interface properties for a link provided to at least one of a plurality of endpoint devices connected to a chipset port/platform connector combination that includes that chipset port and a respective platform connector, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port;
generating, by the chipset port configuration generation subsystem during the first initialization operations, a first chipset configuration descriptor using the respective first port configurations; and
configuring, by the chipset port configuration generation subsystem during the first initialization operations, the plurality of chipset ports using the first chipset port configuration descriptor.
15. The method of claim 14 , wherein the chipset port configuration generation subsystem is provided by a Basic Input Output System (BIOS).
16. The method of claim 14 , wherein the determining the respective first port configuration for each of the plurality of chipset ports includes:
determining, by the chipset port configuration generation subsystem during the first initialization operations, a number of the plurality of endpoint devices connected via the respective platform connector to that chipset port; and
bifurcating, by the chipset port configuration generation subsystem during the first initialization operations, that chipset port based on the number of the plurality of endpoint devices connected via the respective platform connector to that chipset port.
17. The method of claim 14 , wherein the respective first port configuration for each of the plurality of chipset ports is selected from chipset capability information that is included in the chipset port configuration generation subsystem and that identifies the capabilities of each of the plurality of chipset ports.
18. The method of claim 14 , wherein the respective first port configuration for each of the plurality of chipset ports includes at least one of a hotplug configuration, a power configuration, a lane configuration, and a bifurcation configuration.
19. The method of claim 14 , further comprising:
determining, by the chipset port configuration generation subsystem during second initialization operations, a respective second port configuration for each of the plurality of chipset ports based on 1) a plurality of second desired interface properties for the link provided to the at least one of the plurality of endpoint devices provided to the at least one of the plurality of endpoint devices connected to the chipset port/platform connector combination that includes that chipset port, and 2) capabilities of each of that chipset port and the respective platform connector connected to that chipset port, wherein at least one of the respective second port configurations is different than at least one of the respective first port configurations;
generating, by the chipset port configuration generation subsystem during second initialization operations, a second chipset configuration descriptor using the respective second port configurations, wherein the second chip set configuration descriptor is different than the first chipset configuration descriptor; and
configuring, by the chipset port configuration generation subsystem during second initialization operations, the plurality of chipset ports using the second chipset port configuration descriptor.
20. The method of claim 19 , wherein the at least one of the respective second port configurations is different than the at least one of the respective first port configurations based on a change in the connection of the at least one of the plurality of endpoint devices to at least one of the chipset port/platform connector combinations.