Granted Patent B1

US 11,455,924 · App. 17/390,114 · Granted Sep 27, 2022

Inventors: Jong Seo Lee (Austin, TX); Asim Siddiqui (Cedar Park, TX)

Assignee: Dell Products L.P.

G09G3/006G09G3/3685G09G2310/08G09G2330/10G09G2330/12G09G2370/00

Abstract

Claims (60)

1. A liquid crystal display (LCD) device, comprising:

an LCD panel including a first plurality of pixel data inputs and a first failure sensing circuit, wherein the first pixel data inputs are each coupled to associated columns of first pixel elements, and wherein the first failure sensing circuit is configured to provide a first failure indication on a first output of the LCD panel;

a first source driver configured to drive first pixel data onto the first pixel data inputs, wherein in a first test mode, the first source driver is configured to drive a first voltage onto all of the first pixel data inputs; and

a timing controller coupled to the first source driver by a pixel data link, the timing controller configured to provide the first pixel data to the first source driver via the pixel data link;

wherein in the first test mode, the first failure indication includes the first voltage when the LCD panel has no failures on any of the first pixel elements, and the first failure indication includes any other second voltage when the LCD panel has at least one failing first pixel element, wherein the at least one failing first pixel element is in a high impedance state; and

wherein in a second test mode, the timing controller is configured to initiate a pixel data link test signal via the pixel data link, and the first source driver is further configured to provide a second failure indication indicating a failure on the pixel data link.

2. The LCD device of claim 1 , wherein the at least one failing pixel element includes a shorted pixel element.

3. The LCD device of claim 1 , wherein the first failure indication is provided on the first output of the LCD panel to an input of the first source driver.

4. The LCD device of claim 3 , wherein the first source driver includes a communication interface, and is configured to receive a command on the communication interface to enter the first test mode.

5. The LCD device of claim 4 , wherein the first source driver provides a response to the command, the response including a status of the first failure indication.

6. The LCD device of claim 1 , wherein:

the LCD panel further includes a second plurality of pixel data inputs and a second failure sensing circuit, wherein the second pixel data inputs are each coupled to associated columns of second pixel elements, and wherein the second failure sensing circuit is configured to provide a third failure indication on a second output of the LCD panel;

the LCD device further comprises:

a second source driver configured to drive second pixel data onto the second pixel data inputs, wherein, in the first test mode, the second source driver is configured to drive the first voltage onto all of the second pixel data inputs; and

in the first test mode, the third failure indication includes the first voltage when the LCD panel has no failures on any of the second pixel elements, and the third failure indication includes any other second voltage when the LCD panel has at least one failing second pixel element.

7. The LCD device of claim 1 , further comprising:

a timing controller configured to provide the first pixel data to the first source driver.

8. The LCD device of claim 7 , wherein the first failure indication is provided on the first output of the LCD panel to an input of the timing controller.

9. The LCD device of claim 8 , wherein the timing controller includes a communication interface, and is configured to receive a command on the communication interface to enter the first test mode.

10. The LCD device of claim 9 , wherein the timing controller provides a response to the command, the response including a status of the first failure indication.

11. A method of detecting failure in a liquid crystal display (LCD) device, the method comprising:

providing, in an LCD panel of the LCD display, a first plurality of pixel data inputs and a first failure sensing circuit, wherein the first pixel data inputs are each coupled to associated columns of first pixel elements, and wherein the first failure sensing circuit is configured to provide a first failure indication on a first output of the LCD panel;

driving, by a first source driver of the LCD device, first pixel data onto the first pixel data inputs;

providing, by a timing controller of the LCD device coupled to the first source driver by a pixel data link, the first pixel data to the first source driver via the pixel data link;

driving, by the first source driver in a first test mode, a first voltage onto all of the first pixel data inputs;

providing, in the first test mode, the first voltage on the first output when the LCD panel has no failures on any of the first pixel elements;

providing, in the first test mode, any other second voltage when the LCD panel has at least one failing first pixel element, wherein the at least one failing first pixel element is in a high impedance state;

initiating, by the timing controller in a second test mode, a pixel data link test signal via the pixel data link; and

providing, by the first source driver in the second test mode, a second failure indication indicating a failure on the pixel data link.

12. The method of claim 11 , further comprising:

providing the first failure indication on the first output of the LCD panel to an input of the first source driver.

13. The method of claim 12 , further comprising:

providing, on the first source driver, a communication interface; and

receiving a command on the communication interface to enter the first test mode.

14. The method of claim 13 , further comprising:

providing, by the first source driver, a response to the command, the response including a status of the first failure indication.

15. The method of claim 11 , wherein:

providing, in the LCD panel, a second plurality of pixel data inputs and a second failure sensing circuit, wherein the second pixel data inputs are each coupled to associated columns of second pixel elements, and wherein the second failure sensing circuit is configured to provide a third failure indication on a second output of the LCD panel; and

driving, by a second source driver of the LCD device, the first pixel data onto the first pixel data inputs;

driving, by the second source driver in a first test mode, the first voltage onto all of the first pixel data inputs;

providing, in the first test mode, the first voltage on the second output when the LCD panel has no failures on any of the second pixel elements: and

providing, in the first test mode, any other second voltage when the LCD panel has at least one failing second pixel element.

16. The method of claim 11 , further comprising:

providing, by a timing controller of the LCD device, the first pixel data to the first source driver.

17. The method of claim 16 , further comprising:

providing the first failure indication on the first output of the LCD panel to an input of the timing controller.

18. The method of claim 17 , further comprising:

providing, on the timing controller, a communication interface; and

receiving a command on the communication interface to enter the first test mode.

19. The method of claim 18 , further comprising:

providing, by the timing controller, a response to the command, the response including a status of the first failure indication.

20. An information handling system, comprising:

a processor; and

a liquid crystal display (LCD) device including:

an LCD panel including a first plurality of pixel data inputs and a first failure sensing circuit, wherein the first pixel data inputs are each coupled to associated columns of first pixel elements, and wherein the first failure sensing circuit is configured to provide a first failure indication on a first output of the LCD panel;

a first source driver configured to drive first pixel data onto the first pixel data inputs, wherein, in a first test mode, the first source driver is configured to drive a first voltage onto all of the first pixel data inputs; and

a timing controller coupled to the first source driver by a pixel data link, the timing controller configured to provide the first pixel data to the first source driver via the pixel data link;

wherein, in the first test mode, the first failure indication includes the first voltage when the LCD panel has no failures on any of the first pixel elements, and the first failure indication includes any other second voltage when the LCD panel has at least one failing first pixel element, wherein the at least one failing first pixel element is in a high impedance state;

wherein the processor directs the LCD device to enter the first test mode; and

wherein in a second test mode, the timing controller is configured to initiate a pixel data link test signal via the pixel data link, and the first source driver is further configured to provide a second failure indication indicating a failure on the pixel data link.

Assignments (8)