Gateway device with clock speed that reduces electro-magnetic noise

1. A gateway device comprising:

a radio configured to operate in a 2.4 GHz Wi-Fi band to wirelessly communicate with a client device;

a 32 bit double data rate (DDR) memory having instructions stored therein;

a system clock configured to operate at a clock frequency of 533 MHz; and

a processor configured to execute the instructions stored on said memory to cause said gateway device to:

operate said 32 bit DDR memory at 1067 MHz to fall between harmonics of the system clock;

provide at least 20 megabits throughput at greater than 10 decibels of attenuation;

instruct said radio to transmit data to be transmitted in the 2.4 GHz Wi-Fi band that is not impacted by the clock frequency; and

instruct said radio to receive data to be received in the 2.4 GHz Wi-Fi band that is not impacted by the clock frequency.

2. The gateway device of claim 1 , wherein said 32 bit DDR memory is additionally configurable to operate at 1600 MHz with a second system clock configured to operate at 800 MHz.

3. The gateway device of claim 1 , wherein said gateway device comprises a network access point.

4. The gateway device of claim 1 , wherein said gateway device comprises a router.

5. A method of using a gateway device, said method comprising:

operating a system clock at a clock frequency of 533 MHz;

operating, via a processor configured to execute instructions stored on a 32 bit double data rate (DDR) memory, the 32 bit DDR memory at 1067 MHz to fall between harmonics of the system clock;

providing, via the processor, at least 20 megabits throughput at greater than 10 decibels of attenuation

instructing, via the processor, a radio to transmit data to be transmitted in a 2.4 GHz Wi-Fi band that is not impacted by the clock frequency, wherein the radio is configured to operate in the 2.4 GHz Wi-Fi band to wireless communicate with a client device; and

instructing, via the processor, the radio to receive data to be received in the 2.4 GHz Wi-Fi band that is not impacted by the clock frequency.

6. The method of claim 5 , wherein the 32 bit DDR memory is additionally configurable to operate at 1600 MHz with a second system clock configured to operate at 800 MHz.

7. The method of claim 5 , wherein the gateway device comprises a network access point.

8. The method of claim 5 , wherein the gateway device comprises a router.

9. A non-transitory, computer-readable media of a gateway device having computer-readable instructions stored thereon, the computer-readable instructions being capable of being read by a processor of the gateway device, wherein the computer-readable instructions are capable of instructing the gateway device to perform the method comprising:

operating a system clock at a clock frequency of 533 MHz;

operating, via the processor configured to execute instructions stored on a 32 bit double data rate (DDR) memory, the 32 bit DDR memory at 1067 MHz to fall between harmonics of the system clock;

provide at least 20 megabits throughput at greater than 10 decibels of attenuation;

instructing, via the processor, a radio to transmit data to be transmitted in a 2.4 GHz Wi-Fi band that is not impacted by the clock frequency, wherein the radio is configured to operate in the 2.4 GHz Wi-Fi band to wireless communicate with a client device; and

instructing, via the processor, the radio to receive data to be received in the 2.4 GHz Wi-Fi band that is not impacted by the clock frequency.

10. The non-transitory, computer-readable media of claim 9 , wherein the computer-readable instructions are capable of instructing the gateway device to perform the method wherein the 32 bit DDR memory is additionally configurable to operate at 1600 MHz with a second system clock configured to operate at 800 MHz.

11. The non-transitory, computer-readable media of claim 9 , wherein the gateway device comprises a network access point.

12. The non-transitory, computer-readable media of claim 9 , wherein the gateway device comprises a router.