Electrostatic discharge protection device
An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.
1. An electrostatic discharge (ESD) protection device for an integrated circuit, the ESD comprising:
a gate formed over an active well;
a source and a drain formed in the active well on either side of the gate; and
a boundary region formed in the active well between the gate and the source, a conductive type of the boundary region being opposite to a conductive type of the source and the drain,
wherein the boundary region has an effective width for controlling a holding voltage of the ESD higher than an operating voltage.
2. The ESD protection device of claim 1 , further comprising:
a first peripheral well formed in the active well corresponding to an outside portion of the drain; and
a diode region formed in the first peripheral well to be contacted with the drain.
3. The ESD protection device of claim 2 , wherein the active well, the boundary region and the diode region include impurities of a first conductive type, and
the source, drain and the first peripheral well include impurities of a second conductive type being opposite to the first conductive type.
4. The ESD protection device of claim 3 , wherein the impurities of the first conductive type have a p type conductive type and the impurities of the second conductive type have a n type conductive type.
5. The ESD protection device of claim 1 , wherein a depth of the boundary region is same with depths of the source and drain.
6. The ESD protection device of claim 2 , further comprising:
a deep well formed under the active well; and
a second peripheral well formed to surround an edge of the active well.
7. The ESD protection device of claim 6 , wherein the active well, the first peripheral well and the second peripheral well include a same depth, and
bottom surfaces of the active well, the first peripheral well and the second peripheral well are contacted with the deep well.
8. The ESD protection device of claim 2 , wherein the gate, the source and the active well are electrically connected with a ground terminal, and the diode region is electrically connected with a pad to which a bias is applied.
9. The ESD protection device of claim 2 , further comprising:
an ohmic contact pattern formed on the source and the diode region, respectively.
10. An electrostatic discharge (ESD) protection device for an integrated circuit, the ESD comprising:
a gate formed over an active well with impurities of a first conductive type;
a source and a drain formed in the active well on either side of the gate, the source and the drain including impurities of a second conductive type which is opposite to the first conductive type;
a diode region formed in the active well adjacent and in contact with the drain, the diode region including the impurities of the first conductive type;
a first peripheral well formed under the diode region in the active well, the first peripheral well including the impurities of second conductive type; and
a boundary region including the impurities of the first conductive type formed in the active well between the gate and the source,
wherein the gate, the source and the active well are electrically connected with a ground terminal, and the diode region is electrically connected with a pad to which a bias is applied, and
wherein the boundary region has an effective width for controlling a holding voltage of the ESD higher than an operating voltage.
11. The ESD protection device of claim 10 , further comprising:
a second peripheral well formed to surround an edge of the active well,
wherein the second peripheral well includes the impurities of the second conductive type.
12. The ESD protection device of claim 10 , wherein a depth of the boundary region is same with depths of the source and drain.
13. The ESD protection device of claim 10 , wherein the source does not overlap the gate by the boundary region.
14. The ESD protection device of claim 11 , wherein the active well and the second peripheral well include a well contact region, respectively.
15. The ESD protection device of claim 14 , further comprising:
an ohmic contact pattern formed on the source, the diode region and the well contact regions, respectively.