IP Library Granted Patent US 11,990,542
Granted Patent B2
US 11,990,542 · App. 17/414,253 · Granted May 21, 2024

Nitride semiconductor device

Inventors: Daisuke Shibata (Kyoto, JP); Satoshi Tamura (Osaka, JP); Masahiro Ogawa (Osaka, JP)
Assignee: PANASONIC HOLDINGS CORPORATION
H01L29/7788H01L29/2003H01L29/205H01L29/7789H01L29/7802
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,990,542
App. No.
17/414,253
Granted
May 21, 2024
Kind
B2
Abstract

A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.

Claims (23)

1. A nitride semiconductor device, comprising:

a substrate;

a first nitride semiconductor layer above the substrate, the first nitride semiconductor layer being of an n-type;

a second nitride semiconductor layer above the first nitride semiconductor layer, the second nitride semiconductor layer being of a p-type;

a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer;

an electron transport layer and an electron supply layer disposed on an inner face of the first opening, in the stated order from a side on which the substrate is located;

a gate electrode above the electron supply layer and covering the first opening;

a second opening at a position distanced from the first opening, the second opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer;

a source electrode covering the second opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the second nitride semiconductor layer; and

a drain electrode on a side of the substrate opposite from a side of the substrate on which the first nitride semiconductor layer is located,

wherein a bottom face of the gate electrode is closer to the drain electrode than a bottom face of the second nitride semiconductor layer is, and

wherein the gate electrode includes:

a metal layer including a metal material; and

a third nitride semiconductor layer between the metal layer and the electron supply layer, the third nitride semiconductor layer being of a p-type,

wherein a bottom face of the third nitride semiconductor layer is closer to the drain electrode than the bottom face of the second nitride semiconductor layer is.

2. The nitride semiconductor device according to claim 1 , further comprising:

a high-resistance layer between the second nitride semiconductor layer and the electron transport layer on the inner face of the first opening, the high-resistance layer having a resistance higher than a resistance of the second nitride semiconductor layer.

3. The nitride semiconductor device according to claim 2 ,

wherein the high-resistance layer is a nitride semiconductor layer containing Fe.

4. The nitride semiconductor device according to claim 1 ,

wherein the first nitride semiconductor layer includes:

a first layer; and

a second layer above the first layer, the second layer having a lower donor concentration than the first layer.

Assignments (2)
CHANGE OF NAME Recorded May 9, 2022
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 059909/0607 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2021
From: SHIBATA, DAISUKE; TAMURA, SATOSHI; OGAWA, MASAHIRO
To: PANASONIC CORPORATION
Reel/Frame 057839/0203 →