IP Library Granted Patent US 12,484,263
Granted Patent B2
US 12,484,263 · App. 17/419,676 · Granted Nov 25, 2025

Transistor device, ternary inverter device including same, and manufacturing method therefor

Inventors: Kyung Rok Kim (Ulsan, KR); Jae Won Jeong (Seoul, KR); Young Eun Choi (Ulsan, KR); Woo Seok Kim (Daegu, KR)
Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
H10D62/102H01L21/26513H10D84/85
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Quick Facts
Patent No.
US 12,484,263
App. No.
17/419,676
Granted
Nov 25, 2025
Kind
B2
Abstract

A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Claims (19)

1 . A transistor device comprising:

a substrate;

a source region provided on the substrate;

a drain region in the substrate, the drain region being spaced apart from the source region in a direction parallel to a top surface of the substrate;

a gate electrode provided on the substrate and between the source region and the drain region;

a gate insulating film interposed between the gate electrode and the substrate; a channel region formed under the gate insulating film;

a well region formed in the substrate and at least partially in direct contact with bottom surfaces of a pair of the source region and the drain region; and

a constant current generating layer directly contacts the pair of the source region and the drain regions, extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, and the constant current generating layer being positioned deeper than the channel but shallower than bottom surfaces of the pair of the source region and the drain regions,

wherein the constant current generating layer generates a constant current between the drain region and the well region, and the constant current is a band-to band tunneling (BTBT) current that flows:

from the source region or the drain region through the constant current generating layer to the well region in the substrate, or

from the well region in the substrate through the constant current generating layer to the source region or the drain region,

wherein the constant current is independent from a gate voltage applied to the gate electrode, wherein the substrate and the constant current generating layer have a first conductivity type, wherein the source region and the drain region have a second conductivity type that is different from the first conductivity type, and

wherein a doping concentration of the constant current generating layer is greater than a doping concentration of the substrate, wherein an electric field is formed between the drain region and the constant current generating layer, and an intensity of the electric field is 10 6 V/cm or greater.

2 . The transistor device of claim 1 , wherein the constant current generating layer is provided between a channel formed on the substrate and a bottom surface of the drain region.

3 . The transistor device of claim 1 , wherein the doping concentration of the constant current generating layer is 3×10 18 cm −3 or greater.

4 . The transistor device of claim 1 , wherein the substrate and the source region have the same voltage.

5 . The transistor device of claim 1 , wherein the well region is formed in the substrate and has the first conductivity type.

6 . The transistor device of claim 1 , further comprising a pair of device isolation regions provided on the well region and spaced apart from each other in a first direction parallel to the top surface of the substrate.

7 . The transistor device of claim 6 , wherein the pair of device isolation regions includes an insulating material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2026
From: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
To: TERNELL CO., LTD.
Reel/Frame 074440/0263 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2021
From: KIM, KYUNG ROK; JEONG, JAE WON; CHOI, YOUNG EUN; KIM, WOO SEOK
To: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
Reel/Frame 056710/0488 →
Priority Claims (2)
KR 10-2018-0174229 · Dec 31, 2018 · national
KR 10-2019-0081519 · Jul 5, 2019 · national
Continuity (1)
Related Publication 20220085155A1 · Mar 17, 2022
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