Transistor element, ternary inverter apparatus comprising same, and method for producing same
A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.
1. A ternary inverter device comprising:
an NMOS transistor device; and
a PMOS transistor device,
wherein each of the NMOS transistor device and the PMOS transistor device comprises:
a well region;
a source region, a drain region and a channel region in the well region, the source region and the drain region are spaced apart from each other in a direction parallel to a top surface of the well region, the channel region is between the source region and the drain region; and
a pair of constant current generating patterns provided adjacent to the source region and the drain region in the well region, respectively, each of the pair of constant current generating patterns extends below a channel region between the source region and the drain region and is spaced apart from the other, and
the pair of constant current generating patterns generate a constant current between the drain region and a lower portion of the well region, and
the drain region of the NMOS transistor device and the drain region of the PMOS transistor device are electrically connected to each other and have a same voltage,
wherein the drain region of the NMOS transistor device and the drain region of the PMOS transistor device have:
a first voltage when the NMOS transistor device has a channel current that is stronger than the constant current and the PMOS transistor device has the constant current that is stronger than its channel current,
a second voltage when the NMOS transistor device has the constant current that is stronger than the channel current and the PMOS transistor device has its channel current that is stronger than the constant current, and
a third voltage when each of the NMOS transistor device and the PMOS transistor device has the constant current that is stronger than each respective channel current,
wherein the second voltage is greater than the first voltage, and the third voltage has a value between the first voltage and the second voltage.
2. The ternary inverter device of claim 1 , wherein each of the NMOS transistor device and the PMOS transistor device further comprises:
a gate electrode provided on the well region; and
a gate insulating film interposed between the gate electrode and the top surface of the well region, and
the constant current is independent from a gate voltage applied to the gate electrode.
3. The ternary inverter device of claim 2 , wherein
the source region of the NMOS transistor device is electrically connected to the well region of the NMOS transistor device and has a same voltage as the well region of the NMOS transistor device, and
the source region of the PMOS transistor device is electrically connected to the well region of the PMOS transistor device, and a same voltage as the well region of the PMOS transistor device.
4. The ternary inverter device of claim 1 , wherein, in each of the NMOS transistor device and the PMOS transistor device, the well region and the pair of constant current generating patterns have conductivity types identical to each other, and a doping concentration of each of the pair of constant current generating patterns is greater than a doping concentration of the well region.
5. The ternary inverter device of claim 4 , wherein, in each of the NMOS transistor device and the PMOS transistor device, the doping concentration of each of the pair of constant current generating patterns is 3×10 18 cm −3 or greater.