IP Library Granted Patent US 12,219,126
Granted Patent B2
US 12,219,126 · App. 17/420,080 · Granted Feb 4, 2025

Combined inter and intra prediction

Inventors: Xiaoyu Xiu (San Diego, CA); Yuwen He (San Diego, CA); Jiancong Luo (Skillman, NJ)
Assignee: InterDigital VC Holdings, Inc.
H04N19/105H04N19/159H04N19/176H04N19/46
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Quick Facts
Patent No.
US 12,219,126
App. No.
17/420,080
Granted
Feb 4, 2025
Kind
B2
Abstract

Systems, methods, and instrumentalities are disclosed for a combined inter and intra prediction, A video coding device may receive a motion vector difference (MMVD) mode indication that indicates whether MMVD mode is used to generate inter prediction of a coding unit (CU). The video coding device may receive a combined inter merge/intra prediction (CUP) indication, for example, when the MMVD mode indication indicates that MMVD mode is not used to generate the inter prediction of the CU, The video coding device may determine whether to use triangle merge mode for the CU, for example, based on the MMVD mode indication and/or the CUP indication. On a condition that the CUP indication indicates that CUP is applied for the CU or the MMVD mode indication indicates that MMVD mode is used to generate the inter prediction, the video coding device may disable the triangle merge mode for the CU.

Claims (65)

1. A device for video decoding, comprising:

a processor configured to:

obtain a combined inter merge-intra prediction (CIIP) indication that indicates whether CIIP is applied for a video block;

determine, based on the CIIP indication, that CIIP is applied for the video block;

determine that triangle merge mode is enabled for a picture that comprises the video block;

determine that a condition for disabling triangle merge mode for the video block is satisfied based on the determination that CIIP is applied for the video block;

disable triangle merge mode for the video block; and

decode the picture based on the disablement of triangle merge mode for the video block.

2. The device of claim 1 , wherein the processor is further configured to, based on the satisfaction of the condition for disabling triangle merge mode for the video block, determine that a triangle merge mode indication for the video block is not signaled in video data.

3. The device of claim 1 , wherein the video block is a first video block, and the processor is further configured to:

obtain a second video block in the picture;

determine that CIIP is not applied for the second video block; and

based at least on determining that CIIP is not applied for the second video block, obtain a triangle merge mode indication for determining whether to use triangle merge mode for the video block.

4. The device of claim 3 , wherein the triangle merge mode indication is obtained at a video block level.

5. A method for video decoding, comprising:

obtaining a combined inter merge-intra prediction (CIIP) indication that indicates whether CIIP is applied for a video block;

determining, based on the CIIP indication, that CIIP is applied for the video block;

determining that triangle merge mode is enabled for a picture that comprises the video block;

determining that a condition for disabling triangle merge mode for the video block is satisfied based on the determination that CIIP is applied for the video block;

disabling triangle merge mode for the video block; and

decoding the picture based on the disablement of triangle merge mode for the video block.

6. The method of claim 5 , further comprising, based on the satisfaction of the condition for disabling triangle merge mode for the video block, determining that a triangle merge mode indication for the video block is not signaled in video data.

7. The method of claim 5 , wherein the video block is a first video block, and the method further comprises:

obtaining a second video block in the picture;

determining that CIIP is not applied for the second video block; and

based at least on determining that CIIP is not applied for the second video block, obtaining a triangle merge mode indication for determining whether to use triangle merge mode for the second video block.

8. The method of claim 7 , wherein the triangle merge mode indication is obtained at a video block level.

9. A device for video encoding, comprising:

a processor configured to:

obtain a video block in a picture;

determine that combined inter merge-intra prediction (CIIP) is applied for the video block;

determine that triangle merge mode is enabled for the picture that comprises the video block;

determine that a condition for disabling triangle merge mode for the video block is satisfied based on the determination that CIIP is applied for the video block;

disable triangle merge mode for the video block; and

encode the picture based on the disablement of triangle merge mode for the video block.

10. The device of claim 9 , wherein the processor is further configured to:

include a CIIP indication for the video block in video data to indicate that CIIP is applied for the video block.

11. The device of claim 9 , wherein the video block is a first video block, and the processor is further configured to:

obtain a second video block in the picture;

determine to disable CIIP for the second video block; and

based at least on determining to disable CIIP for the second video block, include a triangle merge mode indication to indicate whether triangle merge mode is used for the second video block.

12. The device of claim 11 , wherein the triangle merge mode indication is included at a video block level.

13. A method for video encoding, comprising:

obtaining a video block in a picture;

determining that combined inter merge-intra prediction (CIIP) is applied for the video block;

determining that triangle merge mode is enabled for the picture that comprises the video block;

determining that a condition for disabling triangle merge mode for the video block is satisfied based on the determination that CIIP is applied for the video block;

disabling triangle merge mode for the video block; and

encoding the picture based on the disablement of triangle merge mode for the video block.

14. The method of claim 13 , further comprising including a CIIP indication for the video block in video data to indicate that CIIP is applied for the video block.

15. The method of claim 13 , wherein the video block is a first video block, and the method further comprises:

obtaining a second video block in the picture;

determining to disable CIIP for the second video block; and

based at least on determining to disable CIIP for the second video block, including a triangle merge mode indication to indicate whether triangle merge mode is used for the second video block.

16. The method of claim 15 , wherein the triangle merge mode indication is included at a video block level.

17. The device of claim 1 , wherein CIIP is based on a weighted average of an intra-prediction signal and an inter-prediction signal.

18. The device of claim 1 , wherein the processor is further configured to:

determine an intra-prediction signal based on a neighboring sample of the video block;

determine an inter-prediction signal based on a merge candidate associated with the video block;

apply a first weight to the intra-prediction signal to generate a weighted intra-prediction signal;

obtain a second weight based on the first weight;

apply the second weight to the inter-prediction signal to generate a weighted inter-prediction signal; and

determine a weighted average based on the weighted intra-prediction signal and the weighted inter-prediction signal, wherein the picture is decoded based on the weighted average.

19. The device of claim 18 , wherein the intra-prediction signal is determined based on an intra planar mode.

20. The device of claim 9 , wherein the processor is further configured to bypass signaling a triangle merge mode indication for the video block in video data.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2024
From: XIU, XIAOYU; HE, YUWEN; LUO, JIANCONG
To: VID SCALE, INC.
Reel/Frame 069635/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2024
From: VID SCALE, INC.
To: INTERDIGITAL VC HOLDINGS, INC.
Reel/Frame 068284/0031 →
Continuity (2)
Provisional Application 62786653 · Dec 31, 2018
Related Publication 20220070441A1 · Mar 3, 2022
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Cited By (1)
US 12,701,217