Transmitting data signals on separate layers of a memory module, and related methods and apparatuses
Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.
1. A method, comprising:
transmitting a first set of data signals including data to be either read from or written to a single memory device on a first signal layer of a printed circuit board (PCB) to or from the single memory device; and
transmitting a second set of data signals including data to be either read from or written to the single memory device on a second, different signal layer of the PCB to or from the single memory device.
2. The method of claim 1 , wherein transmitting a first set of data signals on a first signal layer comprises transmitting the first set of data signals on a signal layer within two layers of a top layer of the PCB.
3. The method of claim 1 , wherein transmitting a second set of data signals on a second, different signal layer comprises transmitting the second set of data signals on a signal layer within two layers of a bottom layer of the PCB.
4. The method of claim 1 , further comprising:
transmitting the first set of data signals on the first signal layer to the single memory device with reference to a first ground plane adjacent a top layer of the PCB; and
transmitting the second set of data signals on the second, different signal layer to the single memory device with reference to a second ground plane that is adjacent a bottom layer of the PCB.
5. The method of claim 1 , wherein:
transmitting the first set of data signals comprises transmitting even DQ bits of a byte of data on the first signal layer; and
transmitting the second set of data signals comprises transmitting odd DQ bits of the byte of data on the second, different signal layer.
6. The method of claim 1 , wherein the transmitting of the second set of data signals is concurrent with the transmitting of the first set of data signals.
7. An apparatus, comprising:
a printed circuit board (PCB); and
circuitry configured to:
transmit a first set of data signals including data to be either read from or written to a single memory device on a first signal layer of the PCB; and
transmit a second set of data signals including data to be either read from or written to the single memory device on a second, different signal layer of the PCB.
8. The apparatus of claim 7 , wherein the first set of data signals are even DQ bits of a byte of data.
9. The apparatus of claim 8 , wherein the second set of data signals are odd DQ bits of the byte of data.
10. The apparatus of claim 7 , wherein the first signal layer is a third layer of the PCB.
11. The apparatus of claim 7 , wherein the second, different signal layer is a tenth layer of the PCB.
12. The apparatus of claim 7 , further comprising:
a first ground layer adjacent the first signal layer, wherein the first set of data signals are referenced with respect to the first ground layer while being transmitted to the single memory device; and
a second ground layer adjacent the second, different signal layer, wherein the second set of data signals are referenced with respect to the second ground layer while being transmitted from an input to a via coupled to the single memory device.
13. The apparatus of claim 12 , wherein the first set of data signals are transmitted to the single memory device while maintaining the reference to the first ground layer, and the second set of data signals are transmitted to the single memory device with no more than a single reference change.
14. The apparatus of claim 7 , wherein the circuitry is further configured to:
transmit even data bits of a byte of data on the first signal layer of a Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) DIMM; and
concurrently transmit even data bits of the byte of data on the second, different signal layer of the DDR4 SDRAM DIMM.
15. An apparatus, comprising:
a first data input layer configured to receive a first set of a first number of data signals including data to be either read from or written to a single memory device;
a first routing layer of a printed circuit board (PCB) coupled to the first data input layer and configured to transmit the first set of the first number of data signals;
a first via coupled between the first routing layer and the single memory device;
a second data input layer configured to receive a second set of the first number of data signals including data to be either read from or written to the single memory device;
a second, different routing layer of the PCB coupled to the second data input layer and configured to transmit the second set of the first number of data signals; and
a second via coupled between second routing layer and the single memory device.
16. The apparatus of claim 15 , further comprising a memory module comprising each of the first data input layer, the first routing layer, the second data input layer, and the second, different routing layer.
17. The apparatus of claim 15 , wherein the first routing layer is configured to transmit a first set of a second number of data signals including data to be either read from or written to a different memory device.
18. The apparatus of claim 17 , wherein the second, different routing layer is configured to transmit a second set of the second number of data signals including data to be either read from or written to the different memory device.
19. The apparatus of claim 15 , wherein the first set of the first number of data signals are even data bits and the second set of the first number of data signals are odd data bits.
20. The apparatus of claim 15 , wherein the first data input layer is a top layer of the PCB, the first routing layer is within two layers of the top layer, the second data input layer is a bottom layer of the PCB, and the second, different routing layer is within two layers of the bottom layer of the PCB.