IP Library Granted Patent US 11,751,323
Granted Patent B2
US 11,751,323 · App. 17/443,742 · Granted Sep 5, 2023

Quad-trace structures for high-speed signaling

Inventors: Sandor Farkas (Round Rock, TX); Bhyrav Mutnury (Austin, TX)
Assignee: Dell Products L.P.
H05K1/0245H05K1/115H05K3/4644H05K1/18H05K2201/09636H05K2201/09672
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Quick Facts
Patent No.
US 11,751,323
App. No.
17/443,742
Granted
Sep 5, 2023
Kind
B2
Abstract

A printed circuit board (PCB) is provided for transmitting a differential signal. The PCB includes first and second conductive signal layers. The first conductive signal layer includes a first positive trace of the differential signal and a first negative trace of the differential signal. The second conductive signal layer includes a second positive trace of the differential signal and a second negative trace of the differential signal. The first positive trace is adjacent to the first negative trace, and the second positive trace is adjacent to the second negative trace and directly below the first negative trace.

Claims (68)

1. A printed circuit board (PCB) for transmitting a differential signal between a first component and a second component, the PCB comprising:

a first conductive signal layer including a first differential signal pair of the differential signal, the first differential signal pair including:

a first positive trace configured to be coupled at a first end to a positive signal contact of the first component;

a second positive trace configured to be coupled at a first end to a second end of the first positive trace and to be coupled at a second end to a first positive signal contact of the second component;

a first negative trace configured to be coupled at a first end to a negative signal contact of the first component; and

a second negative trace configured to be coupled at a first end to a second end of the first negative trace and to be coupled at a second end to a first negative signal contact of the second component, the second positive trace being adjacent to the second negative trace;

a second conductive signal layer;

a first positive via between the first conductive layer and the second conductive signal layer, the first positive via being coupled to the second end of the first positive trace and to the first end of the second positive trace; and

a first negative via between the first conductive signal layer and the second conductive signal layer, the first negative via being coupled to the second end of the first negative trace and to the first end of the second negative trace;

the second conductive signal layer including a second differential signal pair of the differential signal, the second differential signal pair including:

a third positive trace coupled at a first end to the first positive via and configured to be coupled at a second end to a second positive signal contact of the second component; and

a third negative trace coupled at a first end to the negative via and configured to be coupled at a second end to a second negative signal contact of the second component, the third positive trace being adjacent to the third negative trace.

2. The PCB of claim 1 , further comprising:

a second positive via between the first conductive signal layer and the second conductive signal layer, the second positive via being coupled to the second positive trace at a location between the first positive via and the second end of the second positive trace; and

a second negative via between the first conductive signal layer and the second conductive signal layer, the second negative via being coupled to the second negative trace at a location between the first negative via and the second end of the second negative trace.

3. The PCB of claim 2 , wherein:

the second positive via is coupled to the second end of the third positive trace; and

the second negative via is coupled to the second end of the third negative trace.

4. The PCB of claim 1 , wherein the first and second conductive signal layers are adjacent conductive signal layers.

5. The PCB of claim 4 , wherein the first and second conductive signal layers are separated by an insulating layer of the PCB.

6. The PCB of claim 5 , wherein the insulting layer includes one of a prepregnated fiberglass layer, a Duroid layer, a FR4 layer, and an epoxy resin layer.

7. The PCB of claim 1 , wherein the first, second, and third positive traces and the first, second, and third negative traces are formed of one of gold, nickel, tin, and tin-lead.

8. The PCB of claim 1 , wherein;

the third positive trace is substantially directly below the second negative trace; and

the third negative trace is substantially directly below the second positive trace.

9. A method for transmitting a differential signal in a printed circuit board (PCB) between a first component and a second component, the method comprising:

forming a first conductive signal layer in the PCB;

forming a second conductive signal layer in the PCB;

forming a first differential signal pair of the differential signal in the first conductive signal layer, the first differential signal pair including:

a first positive trace configured to be coupled at a first end to a positive signal contact of the first component;

a second positive trace configured to be coupled at a first end to a second end of the first positive trace, and to be coupled at a second end to a first positive signal contact of the second component;

a first negative trace configured to be coupled at a first end to a negative signal contact of the first component; and

a second negative trace configured to be coupled at a first end to a second end of the first negative trace, and to be coupled at a second end to a first negative signal contact of the second component, the second positive trace being adjacent to the second negative trace;

forming a first positive via between the first conductive signal layer and the second conductive signal layer, the first positive via being coupled to the second end of the first positive trace and to the first end of the second positive trace;

forming a first negative via between the first conductive signal layer and the second conductive signal layer, the first negative via being coupled to the second end of the first negative trace and to the first end of the second negative trace; and

forming a second differential signal pair of the differential signal in the second conductive signal layer, the second differential signal pair including:

a third positive trace coupled at a first end to the first positive via and configured to be coupled at a second end to a second positive signal contact of the second component; and

a third negative trace coupled at a first end to the negative via and configured to be coupled at a second end to a second negative signal contact of the second component, the third positive trace being adjacent to the third negative trace.

10. The method of claim 9 , further comprising:

forming a second positive via between the first conductive signal layer and the second conductive signal layer, the second positive via being coupled to the second positive trace at a location between the first positive via and the second end of the second positive trace; and

forming a second negative via between the first conductive signal layer and the second conductive signal layer, the second negative via being coupled to the second negative trace at a location between the first negative via and the second end of the second negative trace.

11. The method of claim 10 , further comprising:

coupling the second positive via to the second end of the third positive trace; and

coupling the second negative via to the second end of the third negative trace.

12. The method of claim 9 , wherein the first and second conductive signal layers are adjacent conductive signal layers.

13. The method of claim 12 , wherein the first and second conductive signal layers are separated by an insulating layer of the PCB, and wherein the insulting layer includes one of a prepregnated fiberglass layer, a Duroid layer, a FR4 layer, and an epoxy resin layer.

14. The method of claim 9 , wherein the first, second, and third positive traces and the first, second, and third negative traces are formed of one of gold, nickel, tin, and tin-lead.

15. The method of claim 9 , wherein;

the third positive trace is substantially directly below the second negative trace; and

the third negative trace is substantially directly below the second positive trace.

16. An information handling system, comprising:

a first component;

a second component; and

a printed circuit board (PCB) for transmitting a differential signal between a first component and a second component, the PCB including:

a first conductive signal layer including a first differential signal pair of the differential signal, the first differential signal pair including:

a first positive trace configured to be coupled at a first end to a positive signal contact of the first component;

a second positive trace configured to be coupled at a first end to a second end of the first positive trace, and to be coupled at a second end to a first positive signal contact of the second component;

a first negative trace configured to be coupled at a first end to a negative signal contact of the first component; and

a second negative trace configured to be coupled at a first end to a second end of the first negative trace, and to be coupled at a second end to a first negative signal contact of the second component, the second positive trace being adjacent to the second negative trace; and

a second conductive signal layer;

a first positive via between the first conductive signal layer and the second conductive signal layer, the first positive via being coupled to the second end of the first positive trace and to the first end of the second positive trace; and

a first negative via between the first conductive signal layer and the second conductive signal layer, the first negative via being coupled to the second end of the first negative trace and to the first end of the second negative trace;

the second conductive signal layer including a second differential signal pair of the differential signal, the second differential signal pair including:

a third positive trace coupled at a first end to the first positive via and configured to be coupled at a second end to a second positive signal contact of the second component; and

a third negative trace coupled at a first end to the negative via and configured to be coupled at a second end to a second negative signal contact of the second component, the third positive trace being adjacent to the third negative trace.

17. The information handling system of claim 16 , wherein;

the third positive trace is substantially directly below the second negative trace; and

the third negative trace is substantially directly below the second positive trace.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (058014/0560) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0473 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057931/0392) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0382 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057758/0286) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 061654/0064 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 058014/0560 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057758/0286 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057931/0392 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2021
From: FARKAS, SANDOR; MUTNURY, BHYRAV
To: DELL PRODUCTS, LP
Reel/Frame 056994/0640 →
Continuity (1)
Related Publication 20230031615A1 · Feb 2, 2023