IP Library Granted Patent US 11,972,120
Granted Patent B2
US 11,972,120 · App. 17/443,962 · Granted Apr 30, 2024

System and method of forecasting an amount of time a solid state drive can be unpowered

Inventor: Anthony Gerard Ginty (Cork, IE)
Assignee: Dell Products L.P.
G06F3/0625G06F3/0655G06F3/0679
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Quick Facts
Patent No.
US 11,972,120
App. No.
17/443,962
Granted
Apr 30, 2024
Kind
B2
Abstract

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive a scaling factor and a retention time power law coefficient associated with a solid state drive (SSD); determine a first raw bit error rate (RBER) value for the SSD at a first time; extrapolate a second time at which a second RBER value for the SSD would reach a maximum RBER value if left unpowered, based at least on the first raw bit error rate value, the scaling factor, and the retention time power law coefficient; and provide the second time at which the second RBER value for the SSD would reach the maximum raw bit error rate value if left unpowered to at least one of an information handling system (IHS), IHS firmware, a baseboard management controller of the IHS, and an application executing on the IHS.

Claims (67)

1. An information handling system, comprising:

at least one processor;

a memory medium, coupled to the at least one processor, storing instructions executable by the at least one processor;

a first solid state drive coupled to the at least one processor and including at least one first non-volatile storage device; and

a second solid state drive coupled to the at least one processor and including at least one second non-volatile storage device, wherein the second solid state drive is physically different from the first solid state drive;

wherein the first solid state drive is configured to:

determine a first raw bit error rate value of the first solid state drive at a first time; and

determine, based on the first raw bit error rate value of the first solid state drive, a scaling factor associated with the first solid state drive and a retention time power law coefficient associated with the first solid state drive;

wherein the second solid state drive is configured to:

receive the scaling factor associated with the first solid state drive and the retention time power law coefficient associated with the first solid state drive; and

extrapolate a time at which a second raw bit error rate value for the second solid state drive would reach a maximum raw bit error rate value if left unpowered, based at least on the first raw bit error rate value, the scaling factor associated with the first solid state drive, and the retention time power law coefficient associated with the first solid state drive;

wherein the instructions, which when executed by the at least one processor, cause the information handling system to:

query the second solid state drive for the extrapolated time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered; and

wherein the second solid state drive is further configured to:

provide the extrapolated time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered to at least one of the information handling system, information handling system firmware, a baseboard management controller of the information handling system, and an application executing on the information handling system;

maintain data at the second solid state drive up to the extrapolated time when the second solid state drive is left unpowered; and

perform, by a controller of the second solid state drive, an error correction process of the data prior to the extrapolated time.

2. The information handling system of claim 1 , wherein the at least one first non-volatile storage device includes at least one NAND flash storage device.

3. The information handling system of claim 2 , wherein the at least one NAND flash storage device includes at least one of a triple-level cell (TLC) NAND flash memory and a quad-level cell (QLC) NAND flash memory.

4. The information handling system of claim 1 , wherein the second solid state drive is further configured to receive a query for the extrapolated time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered.

5. The information handling system of claim 1 , wherein, to extrapolate the time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered, the second solid state drive is further configured to:

determine t as the extrapolated time at which the second raw bit error rate for the second solid state drive would reach the maximum raw bit error rate value if left unpowered from an equation:

RBER( t )=RBER 0 +( S·t m ),

utilizing the scaling factor associated with the first solid state drive as S, the retention time power law coefficient as m, the maximum raw bit error rate value as RBER(t), and the raw bit error rate value for the first solid state drive at the first time as RBER 0 .

6. The method of claim 1 , wherein, when the second solid state drive reaches the maximum raw bit error rate value, an error correction process of the second solid state drive can no longer correct errors caused by utilization of the second solid state drive.

7. A method, comprising:

determining, by a first solid state drive, a first raw bit error rate value at a first time of the first solid state drive, wherein the first solid state drive has reached a maximum number of program-erase cycles;

determining a plurality of raw bit error rate values of the first solid state drive at a plurality of respective times after the first time;

determining, by the first solid state drive and based on the plurality of raw bit error values of the first solid state drive, a scaling factor associated with the first solid state drive and a retention time power law coefficient associated with the first solid state drive;

receiving, by a controller of a second solid state drive, the scaling factor associated with the first solid state drive and the retention time power law coefficient associated with the first solid state drive, wherein the second solid state drive is physically different from the first solid state drive;

determining, by the controller of the second solid state drive, a second raw bit error rate value for the second solid state drive at a second time;

extrapolating, by the controller of the second solid state drive, a time at which a third raw bit error rate for the second solid state drive would reach a maximum raw bit error rate value if left unpowered, based at least on the second raw bit error rate value, the scaling factor associated with the first solid state drive, and the retention time power law coefficient associated with the first solid state drive;

providing, by the controller of the second solid state drive, the extrapolated time at which the third raw bit error rate for the second solid state drive would reach the maximum raw bit error rate value if left unpowered to at least one of an information handling system, information handling system firmware, a baseboard management controller of the information handling system, and an application executing on the information handling system;

maintaining data at the second solid state drive for up to the extrapolated time when the second solid state drive is left unpowered; and

performing, by the controller of the second solid state drive, an error correction process of the data prior to the extrapolated time.

8. The method of claim 7 , wherein the second solid state drive includes at least one NAND flash storage device.

9. The method of claim 8 , wherein the at least one NAND flash storage device includes at least one of a triple-level cell (TLC) NAND flash memory and a quad-level cell (QLC) NAND flash memory.

10. The method of claim 7 , wherein the determining the scaling factor associated with the first solid state drive and the retention time power law coefficient associated with the first solid state drive includes curve fitting the first raw bit error rate value (RBER 0 ) and the plurality of raw bit error rate values (RBER(t) values) to an equation:

RBER( t )=RBER 0 +( S·t m )

to determine the scaling factor associated with the first solid state drive as S and the retention time power law coefficient as m.

11. The method of claim 10 , further comprising:

setting, by the controller of the second solid state drive, RBER(t) of the equation to the maximum raw bit error rate value; and

determining, by the controller of the second solid state drive, t as the extrapolated time at which the third raw bit error rate for the second solid state drive would reach the maximum raw bit error rate value if left unpowered.

12. The method of claim 7 , wherein, when the second solid state drive reaches the maximum raw bit error rate value, an error correction process of the second solid state drive can no longer correct errors caused by utilization of the second solid state drive.

13. A computing environment, comprising:

a first solid state drive, including:

a controller; and

at least one non-volatile storage device coupled to the controller of the first solid state drive;

wherein the controller of the first solid state drive is configured to:

determine a first raw bit error rate value of the first solid state drive at a first time; and

determine, based on the first raw bit error rate value of the first solid state drive, a scaling factor associated with the first solid state drive and a retention time power law coefficient associated with the first solid state drive;

a second solid state drive, including:

a controller; and

at least one non-volatile storage device coupled to the controller of the second solid state drive;

wherein the controller of the second solid state drive is configured to:

receive the scaling factor associated with the first solid state drive and the retention time power law coefficient associated with the first solid state drive, the second solid state drive is physically different from the first solid state drive;

extrapolate a time at which a second raw bit error rate value of the second solid state drive would reach a maximum raw bit error rate value if left unpowered, based at least on the first raw bit error rate value, the scaling factor associated with the first solid state drive, and the retention time power law coefficient associated with the first solid state drive;

provide the extrapolated time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered to at least one of an information handling system, information handling system firmware, a baseboard management controller of the information handling system, and an application executing on the information handling system;

maintain data at the second solid state drive for up to the extrapolated time when the second solid state drive is left unpowered; and

perform, by the controller of the second solid state drive, an error correction process of the data prior to the extrapolated time.

14. The computing environment of claim 13 , wherein the at least one non-volatile storage device of the second solid state drive includes at least one NAND flash storage device.

15. The computing environment of claim 14 , wherein the at least one NAND flash storage device includes at least one of a triple-level cell (TLC) NAND flash memory and a quad-level cell (QLC) NAND flash memory.

16. The computing environment of claim 13 , wherein, to extrapolate the time at which the second raw bit error rate value for the second solid state drive would reach the maximum raw bit error rate value if left unpowered, the controller of the second solid state drive is further configured to:

determine t as the extrapolated time at which the second raw bit error rate for the second solid state drive would reach the maximum raw bit error rate value if left unpowered from an equation:

RBER( t )=RBER 0 +( S·t m ),

utilizing the scaling factor associated with the first solid state drive as S, the retention time power law coefficient as m, the maximum raw bit error rate value as RBER(t), and the first raw bit error rate value for the first solid state drive at the first time as RBER 0 .

17. The computing environment of claim 13 , wherein the controller of the second solid state drive is further configured to receive a query for the extrapolated time at which the second raw bit error rate for the second solid state drive would reach the maximum raw bit error rate value if left unpowered.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (058014/0560) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0473 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057931/0392) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0382 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057758/0286) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 061654/0064 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 058014/0560 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057758/0286 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057931/0392 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2021
From: GINTY, ANTHONY GERARD
To: DELL PRODUCTS L.P.
Reel/Frame 057016/0201 →
Continuity (1)
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