Reduced complexity decoder with improved error correction and related systems methods and devices

1. An apparatus comprising:

a terminal provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits, the bits corresponding to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values; and

a processing circuitry to:

pass the LLR messages between check nodes and message nodes, the message nodes corresponding to the bits, the check nodes corresponding to parity check equations of a parity check matrix; and

saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages at a start of each sub-iteration of passing the LLR messages between the check nodes and the message nodes.

2. The apparatus of claim 1 , wherein the known bits of the LDPC frame comprise a last ninety-seven bits of the LDPC frame before parity vectors of the LDPC frame.

3. The apparatus of claim 1 , wherein the highest magnitude value corresponds to highest level of certainty conveyable by the LLR messages that a corresponding bit has a zero value.

4. The apparatus of claim 3 , wherein the highest magnitude value is +31.75.

5. The apparatus of claim 1 , wherein the known bits have a logic value of zero.

6. A method of decoding a low density parity check (LDPC) frame, the method comprising:

receiving, at a physical layer device, the LDPC frame including known bits and unknown bits, the known bits having known values;

passing log-likelihood ratio (LLR) messages between check nodes and message nodes, the message nodes corresponding to the known bits and the unknown bits, the check nodes corresponding to parity check equations of a parity check matrix, the LLR messages indicating probabilities that the known bits and the unknown bits have predetermined logic values; and

saturating LLR values of at least a portion of the LLR messages corresponding to the known bits to a highest possible magnitude at a start of each sub-iteration of passing the LLR messages between the check nodes and the message nodes.

7. The method of claim 6 , comprising correcting the LDPC frame responsive to the passing of the LLR messages between the check nodes and the message nodes.

8. The method of claim 6 , wherein the known values of the known bits are zeros.

9. The method of claim 6 , wherein saturating the LLR values of at least portion of the LLR messages corresponding to the known bits to the highest possible magnitude includes saturating the LLR values of all the LLR messages corresponding to the known bits to the highest possible magnitude.

10. An apparatus, comprising:

a terminal to receive a low density parity check (LDPC) frame, the LDPC frame including bits having log likelihood ratio (LLR) values associated therewith, a portion of the bits having known values, the LLR values indicating probabilities that the bits have predetermined logic values; and

a processing circuitry to:

correct bits of the LDPC frame using message nodes and check nodes responsive to at least the LLR values, the message nodes corresponding to the bits, the check nodes corresponding to parity check equations of a parity check matrix; and

saturate a subset of the LLR values corresponding to the portion of the bits having the known values to a highest possible magnitude at a start of each sub-iteration.

11. The apparatus of claim 10 , wherein the known values are zeros.

12. The apparatus of claim 10 , wherein the LDPC frame includes:

a first data part including message bits; and

a second data part including the portion of the bits having the known values.

13. The apparatus of claim 12 , wherein each of the message bits contributes to six of the check nodes.

14. The apparatus of claim 10 , wherein the LDPC frame includes a first parity vector and a second parity vector.