Power and area efficient digital-to-time converter with improved stability
A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
1. A circuit, comprising:
a charging capacitor including a common terminal;
a switched capacitor voltage-to-current converter configured to convert a reference voltage into a first current;
a current mirror configured to convert the first current into a second current and to provide the second current to charging capacitor through the common terminal; and
a comparator having a first input terminal coupled to the common terminal.
2. The circuit of claim 1 , wherein the current mirror includes:
a first switch coupled between the current mirror and the common terminal, the first switch being configured to close responsive to a timing signal.
3. The circuit of claim 2 , wherein the switched capacitor voltage-to-current converter includes:
a first transistor; and
an error amplifier having an output terminal coupled to a gate of the first transistor, wherein the current mirror includes a diode-connected transistor in series with the first transistor and a second transistor having a gate connected to a gate of the diode-connected transistor.
4. The circuit of claim 3 , wherein the first switch is coupled between the common terminal and the second transistor.
5. The circuit of claim 3 , wherein the switched capacitor voltage-to-current converter further includes:
a degeneration resistor coupled between ground and a source of the first transistor.
6. The circuit of claim 3 , wherein the switched capacitor voltage-to-current converter further includes:
an auto-zero switch coupled between the output terminal of the error amplifier and an input terminal to the error amplifier.
7. The circuit of claim 3 , further comprising:
at least one resistor; and
a current source configured to drive the at least one resistor with a reference current to generate the reference voltage.
8. The circuit of claim 7 , wherein the at least one resistor comprises a voltage divider.
9. The circuit of claim 8 , wherein the charging capacitor comprises a capacitive digital-to-analog converter.
10. The circuit of claim 9 , wherein the voltage divider comprises a first resistor coupled to a second resistor through a node, the circuit further comprising:
a second switch coupled between the node and the capacitive digital-to-analog converter.
11. A method of operation for a digital-to-time converter, comprising:
charging a charging capacitor with an initial voltage responsive to a digital code;
converting a reference voltage into a first current in a switched capacitor voltage-to-current converter;
mirroring the first current into a charging current;
charging a charging capacitor with the charging current after the charging capacitor is charged to the initial voltage; and
determining when a voltage of the charging capacitor equals a trip voltage during the charging of the charging capacitor with the charging current.
12. The method of claim 11 , further comprising:
initiating the charging of the charging capacitor with the charging current responsive to a timing signal.
13. The method of claim 12 , wherein the timing signal is a clock signal and wherein initiating the charging of the charging capacitor with the charging current is responsive to a clock edge of the clock signal.
14. The method of claim 12 , further comprising:
closing a first switch responsive to the timing signal to couple the charging capacitor to the charging current.
15. The method of claim 12 , wherein determining when the voltage of the charging capacitor equals the trip voltage during the charging of the charging capacitor with the charging current is performed in a comparator having an input terminal coupled to the charging capacitor through an auto-zero capacitor, the method further comprising:
charging the auto-zero capacitor to address an offset of the comparator prior to determining when the voltage of the charging capacitor equals the trip voltage.
16. A circuit, comprising:
a capacitive digital-to-analog converter including a plurality of capacitors and a plurality of first switches corresponding to the plurality of capacitors, each first switch in the plurality of first switches being coupled between a common terminal and a respective capacitor in the plurality of capacitors;
a second switch;
a current source coupled to the common terminal through the second switch; and
a comparator having a first input terminal coupled to the common terminal.
17. The circuit of claim 16 , wherein each first switch is a single-pole double-throw switch.
18. The circuit of claim 16 , further comprising:
a third switch coupled between ground and each capacitor in the plurality of capacitors.
19. The circuit of claim 16 , further comprising:
an inverter configured to invert an output signal from the comparator.
20. The circuit of claim 16 , further comprising:
an auto-zero capacitor coupled between the common terminal and the first input terminal.