Semiconductor structure and manufacturing method thereof
Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.
1. A semiconductor structure comprising:
a first conductive structure disposed within a first layer of the semiconductor structure;
a dielectric structure disposed within a second layer of the semiconductor structure, the second layer being disposed on the first layer, wherein the dielectric structure comprises one or more of:
a barrier layer on a bottom surface of the dielectric structure,
a redistribution oxide layer, or
a bonding dielectric layer on a top surface of the dielectric structure;
a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, the second conductive structure having a concave recessed portion on a top surface of the second conductive structure; and
multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.
2. The semiconductor structure of claim 1 , wherein the bonding dielectric layer comprises:
a heterostructure having nitrogen and hydrogen dopants.
3. The semiconductor structure of claim 1 , wherein the second conductive structure comprises a copper interconnect.
4. The semiconductor structure of claim 1 , wherein the multiple layers of conductive material comprise a carbon-based material.
5. The semiconductor structure of claim 1 , wherein a top surface of the multiple layers of conductive material is generally planar with the top surface of the dielectric structure.
6. The semiconductor structure of claim 1 , wherein the
bonding dielectric layer includes one or more recessed portions, and
wherein the semiconductor structure comprises silicon oxynitride material disposed within the one or more recessed portions of the bonding dielectric layer.
7. The semiconductor structure of claim 6 , wherein the one or more recessed portions of the bonding dielectric layer are disposed adjacent to the second conductive structure.
8. The semiconductor structure of claim 1 , wherein a first wafer of the semiconductor structure comprises the first conductive structure, the dielectric structure, the second conductive structure, and the multiple layers of conductive material, and
wherein a second wafer comprises, at a top surface of the second wafer,
an additional dielectric structure bonded to the dielectric structure of the first wafer; and
a third conductive structure bonded to the multiple layers of conductive material of the first wafer.
9. The semiconductor structure of claim 8 , wherein the third conductive structure comprises a metal structure having an additional concave recessed portion, and
an additional conductive material disposed within the additional concave recessed portion.
10. The semiconductor structure of claim 9 , wherein the additional conductive material comprises one or more of:
multiple layers of the additional conductive material, or
a metal nitride material.
11. The semiconductor structure of claim 8 , wherein the third conductive structure of the second wafer and the multiple layers of conductive material of the first wafer comprise:
a same conductive 2-dimensional (2D) layered material,
a heterostructure conductive 2D layered material, or
a metal nitride material.
12. The semiconductor structure of claim 1 , wherein the second conductive structure comprises:
one or more barrier layers comprising 2D layered materials.
13. A semiconductor structure comprising:
a first wafer comprising:
a first dielectric structure that includes a first recessed portion;
a first conductive structure disposed within the first recessed portion, the first conductive structure including a first concave recessed portion on a top surface of the first conductive structure; and
a first conductive material disposed within the first concave recessed portion of the first conductive structure; and
a second wafer comprising:
a second dielectric structure that includes a second recessed portion, the second dielectric structure being bonded to the first dielectric structure;
a second conductive structure disposed within the second recessed portion, the second conductive structure including a second concave recessed portion on a top surface of the second conductive structure; and
a second conductive material disposed within the second concave recessed portion, the second conductive material being bonded to the first conductive material, wherein one or more of the first conductive material or the second conductive material comprises one or more of:
a 2-dimensional layered material, or
a metal nitride material.
14. A method of forming a semiconductor structure, comprising:
depositing a conductive structure within a recessed portion of a dielectric structure, wherein the dielectric structure comprises one or more of:
a barrier layer on a bottom surface of the dielectric structure,
a redistribution oxide layer, or
a bonding dielectric layer on a top surface of the dielectric structure;
polishing a top surface of the semiconductor structure, the polishing forming a concave recessed portion on a top surface of the conductive structure; and
growing a conductive material within the concave recessed portion to form a substantially planar top surface for the semiconductor structure.
15. The method of claim 14 , wherein growing the conductive material within the concave recessed portion comprises one or more of:
depositing multiple 2-dimensional layers of the conductive material within the concave recessed portion, or
growing a metal nitride material, within the concave recessed portion, via ionized metal vapor deposition.
16. The method of claim 14 , wherein depositing the conductive structure, polishing the top surface of the semiconductor structure, and growing the conductive material form a first wafer,
wherein the method further comprises:
forming a second wafer that comprises an additional dielectric structure and an additional conductive material at a bonding interface of the second wafer; and
bonding the second wafer, at the bonding interface of the second wafer, to the first wafer at a top surface of the first wafer,
wherein the conductive material is bonded to the additional conductive material and the dielectric structure is bonded to the additional dielectric structure.
17. The method of claim 16 , wherein bonding the second wafer to the first wafer comprises:
bonding the second wafer to the first wafer at a temperature in a range of approximately 15 degrees Celsius to approximately 25 degrees Celsius.
18. The method of claim 16 , wherein the additional conductive material is grown, within an additional concave recessed portion of an additional conductive structure of the second wafer, via one or more of:
depositing multiple 2-dimensional layers of the additional conductive material within the additional concave recessed portion, or
growing an additional metal nitride material, within the concave recessed portion, via ionized metal vapor deposition.
19. The semiconductor structure of claim 1 , wherein the multiple layers of conductive material comprise one or more of:
a 2-dimensional layered material, or
a metal nitride material.
20. The semiconductor structure of claim 13 , wherein one or more of the first dielectric structure or the second dielectric structure comprise one or more of:
a barrier layer on a bottom surface,
a redistribution oxide layer, or
a bonding dielectric layer on a top surface.