IP Library › Granted Patent US 11,927,869

Granted Patent B2

US 11,927,869 · App. 17/451,339 · Granted Mar 12, 2024

Semiconductor substrate and a display device incorporating the semiconductor substrate

Inventor: Hirotaka Hayashi (Tokyo, JP)

Assignee: Japan Display Inc.

G02F1/16766 G02F1/133345 G02F1/136227 G02F1/167 G02F1/16757 H01L27/1225 H01L27/124 H01L29/7869

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Quick Facts

Patent No.: US 11,927,869
App. No.: 17/451,339
Granted: Mar 12, 2024
Kind: B2

External Links

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Abstract

According to one embodiment, a semiconductor substrate, comprising, a first semiconductor layer and a second semiconductor layer that overlap a scanning line, an insulating layer that covers the first semiconductor layer and the second semiconductor layer, and a signal line, wherein the insulating layer has a first opening including a pair of long sides and a pair of short sides, the long sides of the first opening are parallel to the second direction, and the short sides of the first opening are parallel to the first direction, and the signal line is connected to the first semiconductor layer and the second semiconductor layer via the first opening.

Claims (87)

1. A semiconductor substrate, comprising:

a plurality of scanning lines each of which extends in a first direction;

a plurality of signal lines each of which intersects each of the scanning lines, and extends in a second direction;

a plurality of pixels each of which is portioned by two of the scanning lines and two of the signal lines;

a first semiconductor layer and a second semiconductor layer that overlap each of the scanning lines; and

an insulating layer that covers the first semiconductor layer and the second semiconductor layer on which the plurality of signal lines are provided;

wherein

one pixel of the plurality of pixels comprises the first semiconductor layer and the second semiconductor layer,

the first semiconductor layer and the second semiconductor layer in the one pixel are connected to one of the signal lines corresponding to the one pixel, and overlap to one of the scanning lines corresponding to the one pixel,

the insulating layer includes a first opening including a pair of long sides and a pair of short sides,

the long sides of the first opening are parallel to the second direction, and the short sides of the first opening are parallel to the first direction, and

the one of the signal lines is connected to the first semiconductor layer and the second semiconductor layer via the first opening in the one pixel.

2. The semiconductor substrate according to claim 1 , wherein

the one pixel further comprises a connection electrode and a pixel electrode,

the connection electrode is provided on the insulating layer and parallel to the signal lines,

the pixel electrode is connected to the connection electrode, wherein

the insulating layer includes a second opening that includes a pair of long sides and a pair of short sides in the one pixel,

the second opening is disposed spaced apart from the first opening in the first direction,

the long sides of the second opening are parallel to the second direction, and the short sides of the second opening are parallel to the first direction, and

the connection electrode is connected to the first semiconductor layer and the second semiconductor layer via the second opening.

3. The semiconductor substrate according to claim 1 , wherein

the first semiconductor layer is provided spaced apart from the second semiconductor layer in the one pixel along the second direction, and

the first semiconductor layer and the second semiconductor layer in the one pixel are located between a pair of short sides of the first opening in the second direction.

4. A semiconductor substrate, comprising:

a scanning line that extends in a first direction;

a first insulating layer that is provided on the scanning line;

an oxide semiconductor layer that overlaps the scanning line on the first insulating layer;

a second insulating layer that is provided on the oxide semiconductor layer;

a first opening and a second opening that are provided in the second insulating layer;

a signal line that is provided on the second insulating layer and extends in a second direction intersecting the first direction; and

a connection electrode that is provided on the second insulating layer and extends in the second direction, wherein

the signal line is connected to the oxide semiconductor layer via the first opening,

the connection electrode is connected to the oxide semiconductor layer via the second opening,

the oxide semiconductor layer has a first end portion and a second end portion extending in the second direction,

the first opening has a third end portion and a fourth end portion extending in the second direction,

the second opening has a fifth end portion and a sixth end portion extending in the second direction,

the third end portion and the fifth end portion are opposed to each other and spaced apart from each other in the first direction,

the first end portion is located between the third end portion and the fourth end portion in the first direction, and

the second end portion is located between the fifth end portion and the sixth end portion in the first direction.

5. The semiconductor substrate according to claim 4 , wherein

the signal line has a seventh end portion that overlaps the oxide semiconductor layer and extends in the second direction,

the connection electrode has an eighth end portion that overlaps the oxide semiconductor layer, extends in the second direction, and is opposed to the seventh end portion,

the third end portion is located between the first end portion and the seventh end portion in the first direction, and

the fifth end portion is located between the second end portion and the eighth end portion in the first direction.

6. The semiconductor substrate according to claim 4 , wherein

the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer,

the second oxide semiconductor layer is disposed spaced apart from the first oxide semiconductor layer in the second direction,

the first oxide semiconductor layer has a ninth end portion and a tenth end portion extending along the first direction,

the second oxide semiconductor layer has an eleventh end portion and a twelfth end portion extending along the first direction,

the first opening has a thirteenth end portion and a fourteenth end portion extending along the first direction,

the second opening has a fifteenth end portion and a sixteenth end portion extending along the first direction,

the tenth end portion and the twelfth end portion are opposed to each other and spaced apart from each other in the second direction,

the ninth end portion is located between the tenth end portion and the thirteenth end portion and between the tenth end portion and the fifteenth end portion in the second direction, and

the eleventh end portion is located between the twelfth end portion and the fourteenth end portion and between the twelfth end portion and the sixteenth end portion in the second direction.

7. The semiconductor substrate according to claim 6 , wherein

the first opening overlaps the first oxide semiconductor layer and the second oxide semiconductor layer, and

the second opening overlaps the first oxide semiconductor layer and the second oxide semiconductor layer.

8. A display device, comprising:

a semiconductor substrate that includes a first base, a scanning line that is provided on the first base and extends in a first direction, a first insulating layer that is provided on the scanning line, an oxide semiconductor layer that is provided on the scanning line, a second insulating layer that is provided on the oxide semiconductor layer, a first opening and a second opening that are provided in the second insulating layer, a signal line that is provided on the second insulating layer and extends in a second direction intersecting the first direction, a connection electrode that is provided on the second insulating layer and extends in the second direction, and a pixel electrode that is connected to the connection electrode;

a counter-substrate that includes a second base opposed to the pixel electrode, and a counter-electrode located between the second base and the pixel electrode and opposed to the pixel electrode; and

a display function layer which is located between the pixel electrode and the counter- electrode and to which a voltage applied between the pixel electrode and the counter-electrode is applied, wherein