IP Library Granted Patent US 11,831,340
Granted Patent B2
US 11,831,340 · App. 17/453,119 · Granted Nov 28, 2023

Burst error tolerant decoder and related systems, methods, and devices

Inventor: Peter Graumann (Calgery, CA)
Assignee: Microchip Technology Incorporated
H03M13/2906G06F11/1076H03M13/17
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Quick Facts
Patent No.
US 11,831,340
App. No.
17/453,119
Granted
Nov 28, 2023
Kind
B2
Abstract

Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Claims (22)

1. A transmission interface that is burst-error tolerant, the transmission interface comprising:

a transmitter to sequentially provide a forward error correction (FEC) encoded transmission block to a physical transmission line; and

a receiver to:

receive the FEC encoded transmission block from the physical transmission line;

detect, via multiple candidate correction patterns, bits of the received FEC encoded transmission block that exhibit characteristics indicative of burst errors induced in the FEC encoded transmission block during transmission over the physical transmission line; and

change at least some of the detected bits.

2. The transmission interface of claim 1 , wherein the receiver comprises a burst error decoder, wherein the burst error decoder tests candidate correction patterns for correcting errors in contiguous bits on the received FEC encoded transmission block.

3. The transmission interface of claim 2 , wherein the receiver comprises a standard error correction decoder, wherein the standard error correction decoder applies a standard error correction protocol on the received FEC encoded transmission block, and wherein the receiver selects one of a result of the standard error correction circuitry and a result of the burst error decoder.

4. The transmission interface of claim 3 , wherein the burst error decoder:

applies candidate correction patterns to the received FEC encoded transmission block; and

selects a candidate correction pattern having a closest determined relationship with a burst error.

5. The transmission interface of claim 4 , wherein the burst error decoder:

determines a score of a respective candidate correction pattern at least partially based on a correction result generated at least partially responsive to application of the respective candidate correction pattern to the received FEC encoded transmission block;

determines a score of a further respective candidate correction pattern at least partially based on a correction result generated at least partially responsive to application of the further respective candidate correction pattern to the received FEC encoded transmission block; and

selects a candidate correction pattern from one of the respective candidate correction pattern or the further respective candidate correction pattern.

6. The transmission interface of claim 2 , wherein the detected bits of the received FEC encoded transmission block are contiguous bits.

7. A transmission interface that is burst-error tolerant, the transmission interface comprising,

a transmitter to sequentially provide a forward error correction (FEC) encoded transmission block to a physical transmission line; and

a receiver to:

receive the FEC encoded transmission block from the physical transmission line;

detect, via test candidate correction patterns for correcting errors in contiguous bits on the received FEC encoded transmission block, bits of the received FEC encoded transmission block that exhibit characteristics indicative of partial burst errors induced in the FEC encoded transmission block during transmission over the physical transmission line; and

change at least some of the detected bits.

Continuity (3)
Division 16283634 · Feb 22, 2019
Provisional Application 62739744 · Oct 1, 2018
Related Publication 20220052710A1 · Feb 17, 2022