Methods and systems of differential-signal receivers
Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT− node at a second voltage.
1. A method of operating a differential-signal receiver, the method comprising:
receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver;
clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and
clamping, when the first differential signal is negative, an OUT− node at a second voltage.
2. The method of claim 1 wherein clamping the OUT+ node at the first voltage further comprises:
flowing a first current through a first transistor of a selector circuit and creating a first mirror current flowing away from the OUT+ node to clamp the OUT+ node at the first voltage, the first mirror current based on to the first current; and
refraining from flowing current through a second transistor of the selector circuit, and creating a second mirror current away from the OUT− node, the second mirror current based on the first current.
3. The method of claim 2 wherein clamping the OUT− node at the second voltage further comprises:
flowing a second current through the second transistor of the selector circuit and creating a third mirror current flowing away from the OUT− node to clamp the OUT− node at the second voltage, the third mirror current based on the second current; and
refraining from flowing current through the first transistor of the selector circuit, and creating a fourth mirror current away from the OUT+ node, the fourth mirror current based on the second current.
4. The method of claim 1 further comprising:
receiving a second differential signal on the differential-signal pair, the second differential signal accompanying a common-mode voltage that is negative relative to the reference voltage of the differential-signal receiver;
supplying, by the differential-signal receiver, a bias current to the OUT+ node and supplying a bias current to the OUT− node;
clamping, when the second differential signal is positive, the OUT+ node at a third voltage; and
clamping, when the second differential signal is negative, the OUT− node at a fourth voltage.
5. The method of claim 4 wherein clamping the OUT+ node at the third voltage further comprises:
flowing a first current through a first transistor of a selector circuit and creating a first mirror current flowing away from the OUT+ node to clamp the OUT+ node at the third voltage, the first mirror current based on the first current; and
refraining from flowing current through a second transistor of the selector circuit, and creating a second mirror current away from the OUT− node, the second mirror current based on the first current.
6. The method of claim 5 wherein clamping the OUT− node at the fourth voltage further comprises:
flowing a second current through the second transistor of the selector circuit and creating a third mirror current flowing away from the OUT− node to clamp the OUT− node at the fourth voltage, the second mirror current based on the second current; and
refraining from flowing current through the first transistor of the selector circuit, and creating a fourth mirror current away from the OUT+ node, the fourth mirror current based on the second current.
7. The method of claim 1 further comprising, when the first differential signal across the differential-signal pair is zero and the common-mode voltage is below a first predetermined threshold that is non-zero and positive, clamping the OUT+ node and the OUT− node at a third clamp voltage.
8. The method of claim 7 wherein clamping at the third clamp voltage further comprises:
driving a first bias current having a magnitude to the OUT+ node; and
driving a second bias current having the magnitude to the OUT− node.
9. A differential-signal receiver comprising:
an IN+ terminal, an IN− terminal, an OUT+ node, and an OUT− node;
a first resistor having a first resistance, the first resistor coupled between the IN+ terminal and the OUT+ node;
a second resistor having a second resistance, the second resistor coupled between the IN− terminal and the OUT− node;
a first transistor having a first connection coupled to the OUT+ node, a second connection coupled to a reference voltage, and a control input;
a second transistor having a first connection coupled to the OUT− node, a second connection coupled to the reference voltage, and a control input coupled to the control input of the first transistor; and
a selector circuit defining a plus port coupled to the OUT+ node, a minus port coupled to the OUT− node, and a mirror output coupled to the control input of the first transistor and the control input of the second transistor, wherein the selector circuit is configured to, when a common-mode voltage on the IN+ and the IN− terminal is positive, drive the mirror output proportional to a magnitude of the common-mode voltage.
10. The differential-signal receiver of claim 9 wherein the selector circuit further comprises:
a third transistor having a first connection coupled to a voltage source, a second connection coupled to the mirror output, and a control input coupled to the OUT+ node; and
a fourth transistor having a first connection coupled to the voltage source, a second connection coupled to the mirror output, and a control input coupled to the OUT− node.
11. The differential-signal receiver of claim 10 wherein the third transistor is an N-channel field effect transistor (FET), and the fourth transistor is an N-channel FET.
12. The differential-signal receiver of claim 10 further comprising:
a third resistor coupled between the voltage source and the first connection of the third transistor, the third resistor having a third resistance;
a fourth resistor coupled between the voltage source and the first connection of the fourth transistor, the fourth resistor having a fourth resistance; and
the differential-signal receiver configured to reproduce a differential signal received on the IN+ terminal and the IN− terminal across the first connection of the third transistor and the first connection of the fourth transistor.
13. The differential-signal receiver of claim 9 further comprising a bias circuit, the bias circuit comprising:
a positive-drive output coupled to the OUT+ node;
a negative-drive output coupled to the OUT− node;
a sense input coupled to the mirror output; and
wherein the bias circuit is configured to, when the common-mode voltage is below a predetermined threshold, drive a bias current to the OUT+ node and drive a bias current to the OUT− node, the bias currents proportional to an amount the magnitude of the common-mode voltage is below the predetermined threshold.
14. The differential-signal receiver of claim 9 where first resistance is equal to the second resistance.
15. A light control system comprising:
a light controller defining a differential-signal pair comprising a first conductor and a second conductor;
a driver module coupled to the light controller by way of the differential-signal pair, the driver module including a differential-signal receiver comprising:
an IN+ terminal coupled to the first conductor, an IN− terminal coupled to the second conductor, an OUT+ node, and an OUT− node;
a first resistor having a first resistance, the first resistor coupled between the IN+ terminal and the OUT+ node;
a second resistor having a second resistance, the second resistor coupled between the IN− terminal and the OUT− node;
a first transistor having a first connection coupled to the OUT+ node, a second connection coupled to a reference voltage, and a control input;
a second transistor having a first connection coupled to the OUT− node, a second connection coupled to the reference voltage, and a control input coupled to the control input of the first transistor; and
a selector circuit defining a plus port coupled to the OUT+ node, a minus port coupled to the OUT− node, and a mirror output coupled to the control input of the first transistor, wherein the selector circuit is configured to, when a common-mode voltage on the IN+ and the IN− terminal is positive, drive the mirror output proportional to a magnitude of the common-mode voltage.
16. The light control system of claim 15 wherein the selector circuit further comprises:
a third transistor having a first connection coupled to a voltage source, a second connection coupled to the mirror output, and a control input coupled to the OUT+ node; and
a fourth transistor having a first connection coupled to the voltage source, a second connection coupled to the mirror output, and a control input coupled to the OUT− node.
17. The light control system of claim 16 wherein the third transistor is an N-channel field effect transistor (FET), and the fourth transistor is an N-channel FET.
18. The light control system of claim 16 wherein the differential-signal receiver further comprises:
a third resistor coupled between the voltage source and the first connection of the third transistor, the third resistor having a first matching resistance;
a fourth resistor coupled between the voltage source and the first connection of the fourth transistor, the fourth resistor having a second matching resistance; and
the differential-signal receiver configured to reproduce a differential signal received on the IN+ terminal and the IN− terminal across the first connection of the third transistor and the first connection of the fourth transistor.
19. The light control system of claim 15 wherein the differential-signal receiver further comprises a bias circuit, the bias circuit comprising:
a positive-drive output coupled to the OUT+ node;
a negative-drive output coupled to the OUT− node;
a sense input coupled to the mirror output; and
wherein the bias circuit is configured to, when the common-mode voltage is below a predetermined threshold, drive a bias current to the OUT+ node and drive a bias current to the OUT− node, the bias currents proportional to an amount the magnitude of the common-mode voltage is below the predetermined threshold.
20. The light control system of claim 15 where first resistance is equal to the second resistance.