Self-bypass diode function for gallium arsenide photovoltaic devices
Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
1. A method for forming a semiconductor device, the method comprising:
providing a semiconductor structure, the semiconductor structure including a base layer configured to absorb photons to convert light energy into electrical energy at the device; and
wherein providing the semiconductor structure includes forming an emitter layer in the semiconductor structure, the emitter layer being made of a different material than the base layer and having a higher bandgap than the base layer,
wherein a p-n junction of the semiconductor structure is formed between the emitter layer and the base layer such that under reverse-bias conditions in the resulting device the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner, and
wherein the semiconductor structure includes an intermediate layer between the emitter layer and the base layer, the p-n junction being formed between the emitter layer and the intermediate layer, and a heterojunction being formed between the base layer and the intermediate layer.
2. The method of claim 1 , wherein the bypass function is intrinsic to the p-n junction of the semiconductor device such that the semiconductor device provides the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
3. The method of claim 1 , wherein the base layer is highly doped at about 4×10 17 cm −3 or greater.
4. The method of claim 1 , wherein the base layer is highly doped within a range of about 4×10 17 cm −3 to about 1×10 19 cm −3 , and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
5. The method of claim 1 , wherein the p-n junction is formed at a location offset from the heterojunction in the semiconductor structure by up to about 200 nm.
6. The method of claim 5 , wherein the intermediate layer includes a gradation in material composition, from the material of the base layer to the material of the emitter layer.
7. The method of claim 1 , further comprising separating the semiconductor structure from a growth wafer during an epitaxial lift-off (ELO) process, wherein the ELO process includes etching a sacrificial layer disposed between the semiconductor structure and the growth wafer.
8. The method of claim 1 , wherein the semiconductor device is a photovoltaic device and the base layer includes a Group III-V compound semiconductor.
9. The method of claim 1 , wherein forming the emitter layer includes forming the p-n junction, the p-n junction being a heterojunction.
10. The method of claim 1 , further comprising forming a window layer disposed on a surface of the base layer and away from the emitter layer.
11. A method for forming a semiconductor device, the method comprising:
providing a semiconductor structure including a base layer that absorbs photons to convert light energy into electrical energy at the semiconductor device, with the base layer including a Group III-V compound semiconductor;
forming the semiconductor structure to include an emitter layer that is made of a different material than the base layer and has a higher bandgap than the base layer;
forming a p-n junction within the semiconductor structure between the emitter layer and the base layer such that under reverse-bias conditions of the semiconductor device, the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner;
forming an intermediate layer between the emitter layer and the base layer; and
forming a window layer disposed on a surface of the base layer and away from the emitter layer.
12. The method of claim 11 , wherein the base layer is highly doped within a range of about 4×10 17 cm −3 to about 1×10 19 cm −3 , and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
13. The method of claim 11 , further comprising providing the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
14. The method of claim 11 , further comprising providing a contact layer disposed adjacent to the window layer and a metal layer disposed adjacent to the contact layer.
15. The method of claim 11 , further comprising forming the p-n junction at a location offset from a heterojunction in the semiconductor structure by up to about 200 nm.
16. The method of claim 11 , further comprising forming the p-n junction between the emitter layer and the intermediate layer, and forming a heterojunction between the base layer and the intermediate layer.
17. The method of claim 11 , further comprising forming the intermediate layer to include a gradation in material composition from the material of the base layer to the material of the emitter layer.
18. The method of claim 11 , wherein the p-n junction is a heterojunction.