Efficient data layouts for convolutional neural networks
Systems and methods for efficient implementation of a convolutional layer of a convolutional neural network are disclosed. In one aspect, weight values of kernels in a kernel stack of a convolutional layer can be reordered into a tile layout with tiles of runnels. Pixel values of input activation maps of the convolutional layer can be reordered into an interleaved layout comprising a plurality of clusters of input activation map pixels. The output activation maps can be determined using the clusters of the input activation map pixels and kernels tile by tile.
1. A method implemented by a system of one more processors, the method comprising:
receiving a convolutional layer of a convolutional neural network comprising kernels in a kernel stack, wherein the kernels of the kernel stack are in a tile kernel layout comprising a plurality of kernel tiles of kernel runnels;
receiving input activation maps of the convolutional layer, wherein the input activation maps are in a basic input activation map layout;
reordering pixel values of the input activation maps from the basic input activation map layout into an interleaved input activation map layout comprising a plurality of clusters of input activation map pixels by striding; and
determining output activation maps of the convolutional layer from the plurality of kernel tiles and a plurality of input activation map tiles.
2. The method of claim 1 , wherein reordering the pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprises reordering pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprising the plurality of clusters of input activation map pixels by striding with a stride size of a multiple of a number of the input activation maps.
3. The method of claim 2 , wherein the multiple of the number of the input activation maps is one.
4. The method of claim 2 , wherein the multiple of the number of the input activation maps is a multiple of a register width, the register width corresponding to a size associated with a kernel runnel.
5. The method of claim 1 , wherein a dimension of a kernel is one.
6. The method of claim 1 , wherein the pixel values are contiguous in memory of the system.
7. The method of claim 1 , wherein the output activation maps are in a transposed, interleaved output activation map layout comprising a plurality of clusters of output activation maps.
8. The method of claim 1 , wherein determining the output activation maps comprises:
performing fused-multiply-add operations tile by tile on the plurality of kernel tiles and the plurality of clusters of input activation map pixels.
9. A system comprising one or more processors and non-transitory computer storage media storing instructions that when executed by the one or more processors, cause the one or more processors to:
receive a convolutional layer of a convolutional neural network comprising kernels in a kernel stack, wherein the kernels of the kernel stack are in a tile kernel layout comprising a plurality of kernel tiles of kernel runnels;
receive input activation maps of the convolutional layer, wherein the input activation maps are in a basic input activation map layout;
reorder pixel values of the input activation maps from the basic input activation map layout into an interleaved input activation map layout comprising a plurality of clusters of input activation map pixels by striding; and
determine output activation maps of the convolutional layer from the plurality of kernel tiles and a plurality of input activation map tiles.
10. The system of claim 9 , wherein reordering the pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprises reordering pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprising the plurality of clusters of input activation map pixels by striding with a stride size of a multiple of a number of the input activation maps.
11. The system of claim 10 , wherein the multiple of the number of the input activation maps is one.
12. The system of claim 10 , wherein the multiple of the number of the input activation maps is a multiple of a register width, the register width corresponding to a size associated with a kernel runnel.
13. The system of claim 9 , wherein a dimension of a kernel is one.
14. The system of claim 9 , wherein the pixel values are contiguous in memory of the system.
15. The system of claim 9 , wherein the output activation maps are in a transposed, interleaved output activation map layout comprising a plurality of clusters of output activation maps.
16. The system of claim 9 , wherein determining the output activation maps comprises:
performing fused-multiply-add operations tile by tile on the plurality of kernel tiles and the plurality of clusters of input activation map pixels.
17. Non-transitory computer storage media storing instructions that when executed by a system of one or more processors, cause the one or more processors to:
receive a convolutional layer of a convolutional neural network comprising kernels in a kernel stack, wherein the kernels of the kernel stack are in a tile kernel layout comprising a plurality of kernel tiles of kernel runnels;
receive input activation maps of the convolutional layer, wherein the input activation maps are in a basic input activation map layout;
reorder pixel values of the input activation maps from the basic input activation map layout into an interleaved input activation map layout comprising a plurality of clusters of input activation map pixels by striding; and
determine output activation maps of the convolutional layer from the plurality of kernel tiles and a plurality of input activation map tiles.
18. The computer storage media of claim 17 , wherein reordering the pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprises reordering pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprising the plurality of clusters of input activation map pixels by striding with a stride size of a multiple of a number of the input activation maps.
19. The computer storage media of claim 17 , wherein reordering the pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprises reordering pixel values of the input activation maps from the basic input activation map layout into the interleaved input activation map layout comprising the plurality of clusters of input activation map pixels by striding with a stride size of a multiple of a number of the input activation maps.
20. The computer storage media of claim 17 , wherein the multiple of the number of the input activation maps is one or wherein the multiple of the number of the input activation maps is a multiple of a register width, the register width corresponding to a size associated with a kernel runnel.