Semiconductor Device
The present disclosure provides a semiconductor device. The semiconductor device includes an epitaxial stack including a mesa region and a lower region; a first pad on the lower region and a second pad on the mesa region; a first contact between the epitaxial stack and the first pad; a passivation structure covering the epitaxial stack and including a first opening; and a first metal structure in the first opening and disposed between the first contact and the first pad; wherein the first metal structure includes a first top surface away from the epitaxial stack, and the passivation structure including a second top surface at a position corresponding to the lower region and away from the epitaxial stack, and a first height difference between the first top surface and the second top surface is less than 3 μm and larger than zero; and wherein the first metal structure includes a first width adjacent to the first contact and a second width adjacent to the first pad, and the second width is larger than the first width.
1 . A semiconductor device comprising:
an epitaxial stack comprising a mesa region and a lower region;
a first pad on the lower region and a second pad on the mesa region;
a first contact between the epitaxial stack and the first pad;
a passivation structure covering the epitaxial stack and comprising a first opening; and
a first metal structure in the first opening and disposed between the first contact and the first pad;
wherein the first metal structure comprises a first top surface away from the epitaxial stack, and the passivation structure comprising a second top surface at a position corresponding to the lower region and away from the epitaxial stack, and a first height difference between the first top surface and the second top surface is less than 3 um and larger than zero; and
wherein the first metal structure comprises a first width adjacent to the first contact and a second width adjacent to the first pad, and the second width is larger than the first width.
2 . The semiconductor device according to claim 1 , wherein the second top surface is closer to the lower region than the first top surface to the lower region.
3 . The semiconductor device according to claim 1 , wherein the first pad covers the second top surface of the passivation structure.
4 . The semiconductor device according to claim 1 , wherein the first top surface is closer to the lower region than the second top surface to the lower region.
5 . The semiconductor device according to claim 1 , further comprising a base and a bonding layer between the epitaxial stack and the base.
6 . The semiconductor device according to claim 1 , further comprising a base physically connects to the epitaxial stack.
7 . The semiconductor device according to claim 1 , wherein the passivation structure comprises a second opening, and the semiconductor device further comprises a second metal structure in the second opening; and wherein the second metal structure comprises a third top surface away from the epitaxial stack, and the passivation structure comprises a fourth top surface at a position corresponding to the mesa region and away from the epitaxial stack, and a second height difference between the third surface and the fourth top surface is less than 3 μm and larger than zero.
8 . The semiconductor device according to claim 7 , further comprising a second contact between the mesa region and the second metal structure, wherein the second metal structure comprises a third width adjacent to the second contact and a fourth width adjacent to the second pad, and the fourth width is larger than the third width.
9 . The semiconductor device according to claim 1 , wherein the first contact comprises a first thickness and the first metal structure comprises a second thickness larger than the first thickness.
10 . The semiconductor device according to claim 8 , wherein the passivation structure comprises a third thickness, and the second thickness is smaller than the third thickness.
11 . The semiconductor device according to claim 8 , further comprising a third height difference between the mesa region and the lower region, wherein the first contact comprises a first thickness and the second contact comprises a fourth thickness, and the first thickness is substantially equal to a sum of the third height difference and the fourth thickness.
12 . The semiconductor device according to claim 1 , wherein the epitaxial stack comprises a mesa surface at the mesa region and the first contact comprises a fifth top surface higher than the mesa surface.
13 . The semiconductor device according to claim 1 , further comprising a connector between the first contact and the first metal structure.
14 . The semiconductor device according to claim 13 , wherein the connector comprises a connecting surface away from the epitaxial stack and the epitaxial stack comprises a mesa surface at the mesa region and away from the epitaxial stack, and the connecting surface is higher than the mesa surface.
15 . The semiconductor device according to claim 13 , wherein the connector has a part covered by the passivation structure.
16 . A semiconductor device comprising:
an epitaxial stack comprising a mesa region and a lower region;
a first contact on the lower region and a second contact on the mesa region;
a first pad on the first contact and comprising a first concave portion;
a second pad on the second contact; and
a first metal bump on the first pad and comprising a first bump convex portion.
17 . The semiconductor device according to claim 16 , further comprising a second pad on the second contact and a second metal bump on the second pad, wherein the second pad comprises a second concave portion and the second metal bump comprises a second bump convex portion.
18 . The semiconductor device according to claim 16 , further comprising a connector between the first contact and the first pad, wherein the first contact comprises a first contact width and the connector comprises a connector width, and the connector width is small than the first contact width.
19 . The semiconductor device according to claim 18 , wherein the connector comprises a thickness and the first metal bump comprises a thickness larger than that of the connector.
20 . The semiconductor device according to claim 16 , wherein the first pad comprises a first side surface connecting to the first top surface, and the first metal bump covers the first top surface and the first side surface.