IP Library Granted Patent US 11,778,343
Granted Patent B2
US 11,778,343 · App. 17/456,982 · Granted Oct 3, 2023

Methods and circuitry for improving global shutter efficiency in backside illuminated high dynamic range image sensor pixels

Inventors: Dajiang Yang (San Jose, CA); Sergey Velichko (Boise, ID); Bartosz Piotr Banachowicz (San Jose, CA); Tomas Geurts (Haasrode, BE); Muhammad Maksudur Rahman (Santa Clara, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N25/58H01L27/1464H01L27/14627H01L27/14656H04N25/63
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Quick Facts
Patent No.
US 11,778,343
App. No.
17/456,982
Granted
Oct 3, 2023
Kind
B2
Abstract

An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

Claims (40)

1. An image sensor comprising:

a photodiode in a front side of a substrate and configured to accumulate charge generated by scenery light;

a first storage node configured to store the accumulated charge from the photodiode;

a second storage node configured to store charge generated by parasitic light; and

optical diffracting structures in a back side of the substrate.

2. The image sensor of claim 1 , wherein the optical diffracting structures are configured to distribute the parasitic light evenly between the first and second storage nodes.

3. The image sensor of claim 1 , wherein the optical diffracting structures comprise an array of identically shaped dielectric structures.

4. The image sensor of claim 1 , further comprising:

a metal shield on the back side of the substrate and overlapping with the first and second storage nodes.

5. The image sensor of claim 4 , wherein the optical diffracting structures extend under the photodiode.

6. The image sensor of claim 1 , wherein the optical diffracting structures extend under the photodiode, the first storage node, and the second storage node.

7. The image sensor of claim 6 , wherein the photodiode has a portion that extends under the first and second storage nodes.

8. The image sensor of claim 1 , further comprising:

a first microlens configured to focus light towards the photodiode and at least partially overlaps with the first storage node, and

a second microlens configured to focus light towards the photodiode and at least partially overlaps with the second storage node.

9. The image sensor of claim 1 , wherein the first storage node comprises a first charge storage region configured to store low scenery light signals and a first overflow storage region configured to store high scenery light signals.

10. The image sensor of claim 9 , wherein the second storage node comprises a second charge storage region configured to store low parasitic light signals and a second overflow storage region configured to store high parasitic light signals.

11. The image sensor of claim 1 , further comprising:

circuitry configured to subtract the charge stored in the second storage node from the charge stored in the first storage node.

12. An image sensor, comprising:

a photodiode in a front surface of a substrate;

a first storage gate;

a second storage gate;

a floating diffusion region coupled to the photodiode via the first and second storage gates; and

light diffracting structures in a back surface of the substrate and extending under at least the photodiode.

13. The image sensor of claim 12 , wherein the light diffracting structures are configured to disperse light evenly between the first and second storage gates.

14. The image sensor of claim 12 , further comprising:

a plurality of microlenses over the light diffracting structures.

15. The image sensor of claim 12 , wherein the light diffracting structures extend under the first and second storage gates.

16. The image sensor of claim 12 , further comprising:

an overflow capacitor; and

an anti-blooming gate coupled between the photodiode and the overflow capacitor.

17. The image sensor of claim 12 , wherein the light diffracting structures comprise dielectric structures selected from the group consisting of: an array of pyramidal dielectric structures, an array of conical dielectric structures, an array of funnel-shaped dielectric structures, and an array of triangular-shaped dielectric structures.

18. An apparatus comprising:

a photosensitive element in a front surface of a semiconductor substrate;

a floating diffusion region in the front surface of the semiconductor substrate;

a first storage node coupled between the photosensitive element and the floating diffusion region;

a second storage node coupled between the photosensitive element and the floating diffusion region; and

light diffracting structures in a back surface of the semiconductor substrate and configured to disperse light evenly between the first and second storage nodes.

19. The apparatus of claim 18 , wherein the light diffracting structures comprise dielectric structures selected from the group consisting of: an array of pyramidal dielectric structures, an array of conical dielectric structures, an array of funnel-shaped dielectric structures, and an array of triangular-shaped dielectric structures.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 059032, FRAME 0300 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0502 →
SECURITY INTEREST Recorded Feb 17, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 059032/0300 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2021
From: YANG, DAJIANG; VELICHKO, SERGEY; BANACHOWICZ, BARTOSZ PIOTR; GEURTS, TOMAS; RAHMAN, MUHAMMAD MAKSUDUR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 058243/0135 →