IP Library Granted Patent US 11,662,224
Granted Patent B2
US 11,662,224 · App. 17/461,162 · Granted May 30, 2023

Systems and methods for fail-safe resolver excitation

Inventors: Ihab Nahlus (Indianapolis, IN); Marc R. Engelhardt (Kokomo, IN); Mark R. Keyse (Sharpsville, IN)
Assignee: DELPHI TECHNOLOGIES IP LIMITED
G01D5/2073
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Quick Facts
Patent No.
US 11,662,224
App. No.
17/461,162
Granted
May 30, 2023
Kind
B2
Abstract

A method for fail-safe resolver excitation includes generating a resolver excitation signal and providing the resolver excitation signal to an input of a first resolver control circuit and to an input of a second resolver control circuit. The method also includes, in response to the first resolver control circuit detecting a fault in the resolver excitation signal provided to the first resolver control circuit: biasing, using the first resolver control circuit, a first resolver amplifier; and communicating, via a communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the second resolver control circuit that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit.

Claims (49)

1. A method for fail-safe resolver excitation, the method comprising:

generating a resolver excitation signal;

providing the resolver excitation signal to an input of a first resolver control circuit and to an input of a second resolver control circuit;

in response to the first resolver control circuit detecting a fault in the resolver excitation signal provided to the first resolver control circuit:

biasing, using the first resolver control circuit, a first resolver amplifier; and

communicating, via a communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the second resolver control circuit that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit.

2. The method of claim 1 , wherein the first resolver control circuit is independent from the second resolver control circuit.

3. The method of claim 2 , wherein the first resolver control circuit is disposed on a first silicon component and the second resolver control circuit is disposed on a second component, separate from the first silicon component.

4. The method of claim 1 , further comprising, in response to the first resolver control circuit not detecting a fault in the resolver excitation signal provided to the first resolver control circuit, setting a first switch of the first resolver control circuit to a first position, wherein, in response to the first switch being set to the first position, the resolver excitation signal provided to the first resolver control circuit is provided to the first resolver amplifier.

5. The method of claim 1 , further comprising, in response to the second resolver control circuit detecting a fault in the resolver excitation signal provided to the second resolver control circuit and in response to receiving, by the second resolver control circuit and via the communication bus, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit:

setting a second switch of the second resolver control circuit from a first position to a second position;

doubling, using the second resolver control circuit, a gain of a second resolver amplifier;

providing, via the second switch and to the second resolver amplifier, a second output signal having an output frequency and an amplitude associated with an expected resolver excitation signal corresponding to the resolver excitation signal provided to the second resolver control circuit; and

communicating, via the communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the first resolver control circuit that the second resolver control circuit detected the fault in the resolver excitation signal provided to the second resolver control circuit.

6. The method of claim 1 , further comprising, in response to the second resolver control circuit not detecting the fault in the resolver excitation signal provided to the second resolver control circuit, setting a second switch of the second resolver control circuit to a first position, wherein, in response to the second switch being set to the first position, the resolver excitation signal provided to the second resolver control circuit is provided to a second resolver amplifier.

7. The method of claim 1 , further comprising, in response to receiving, by the second resolver control circuit and via the communication bus between the first resolver control circuit and the second resolver control circuit, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit, doubling, using the second resolver control circuit, a gain of a second resolver amplifier.

8. The method of claim 1 , further comprising, in response to the second resolver control circuit receiving, via the communication bus between the first resolver control circuit and the second resolver control circuit, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit and in response to the second resolver control circuit not detecting the fault in the resolver excitation signal provided to the second resolver control circuit:

doubling, using the second resolver control circuit, a gain of a second resolver amplifier; and

providing, via a second switch of the second resolver control circuit in a first position, the resolver excitation signal provided to the second resolver control circuit to the second resolver amplifier.

9. The method of claim 1 , further comprising, in response to the second resolver control circuit detecting a fault in the resolver excitation signal provided to the second resolver control circuit and in response to an absence of a fault in the resolver excitation signal provided to the first resolver control circuit:

biasing, using the second resolver control circuit, a second resolver amplifier; and

communicating, via the communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the first resolver control circuit that the second resolver control circuit detected the fault in the resolver excitation signal provided to the second resolver control circuit.

10. The method of claim 1 , further comprising, in response to receiving, by the first resolver control circuit, from the second resolver control circuit via the communication bus between the first resolver control circuit and the second resolver control circuit, an indication that the second resolver control circuit detected a fault in the resolver excitation signal provided to the second resolver control circuit:

doubling, using the first resolver control circuit, a gain of the first resolver amplifier; and

providing, via a first switch of the first resolver control circuit in a first position, the resolver excitation signal provided to the first resolver control circuit to the first resolver amplifier.

11. The method of claim 1 , wherein biasing, using the first resolver control circuit, the first resolver amplifier includes fixing the first resolver amplifier to mid-supply.

12. A system for fail-safe resolver excitation, the system comprising:

a controller having a processor and a memory, the memory including instructions that, when executed by the controller, cause the controller to:

generate a resolver excitation signal;

provide the resolver excitation signal to an input of a first resolver control circuit and to an input of a second resolver control circuit;

the first resolver control circuit is configured to, in response to detecting a fault in the resolver excitation signal provided to the first resolver control circuit:

bias a first resolver amplifier; and

communicate, via a communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the second resolver control circuit that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit.

13. The system of claim 12 , wherein the first resolver control circuit is independent from the second resolver control circuit.

14. The system of claim 13 , wherein the first resolver control circuit is disposed on a first silicon component and the second resolver control circuit is disposed on a second component, separate from the first silicon component.

15. The system of claim 12 , wherein the first resolver control circuit, in response to not detecting a fault in the resolver excitation signal provided to the first resolver control circuit, sets a first switch of the first resolver control circuit to a first position, wherein, in response to the first switch being set to the first position, the resolver excitation signal provided to the first resolver control circuit is provided to the first resolver amplifier.

16. The system of claim 12 , wherein the second resolver control circuit, in response to detecting a fault in the resolver excitation signal provided to the second resolver control circuit and in response to receiving, via the communication bus, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit:

sets a second switch of the second resolver control circuit from a first position to a second position;

doubles, using the second resolver control circuit, a gain of a second resolver amplifier;

provides, via the second switch and to the second resolver amplifier, a second output signal having an output frequency and an amplitude associated with an expected resolver excitation signal corresponding to the resolver excitation signal provided to the second resolver control circuit; and

communicates, via the communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the first resolver control circuit that the second resolver control circuit detected the fault in the resolver excitation signal provided to the second resolver control circuit.

17. The system of claim 12 , wherein the second resolver control circuit, in response to not detecting the fault in the resolver excitation signal provided to the second resolver control circuit, sets a second switch of the second resolver control circuit to a first position, wherein, in response to the second switch being set to the first position, the resolver excitation signal provided to the second resolver control circuit is provided to a second resolver amplifier.

18. The system of claim 12 , wherein the second resolver control circuit, in response to receiving, via the communication bus between the first resolver control circuit and the second resolver control circuit, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit, doubles, using the second resolver control circuit, a gain of a second resolver amplifier.

19. The system of claim 12 , wherein the second resolver control circuit, in response to receiving, via the communication bus between the first resolver control circuit and the second resolver control circuit, the indication that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit and in response to not detecting the fault in the resolver excitation signal provided to the second resolver control circuit:

doubles, using the second resolver control circuit, a gain of a second resolver amplifier; and

provides, via a second switch of the second resolver control circuit in a first position, the resolver excitation signal provided to the second resolver control circuit to the second resolver amplifier.

20. The system of claim 12 , wherein the second resolver control circuit, in response to detecting a fault in the resolver excitation signal provided to the second resolver control circuit and in response to an absence of a fault in the resolver excitation signal provided to the first resolver control circuit:

biases a second resolver amplifier; and

communicates, via the communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the first resolver control circuit that the second resolver control circuit detected the fault in the resolver excitation signal provided to the second resolver control circuit.

Assignments (2)
CHANGE OF NAME Recorded Sep 18, 2024
From: DELPHI TECHNOLOGIES IP LIMITED
To: BORGWARNER US TECHNOLOGIES LLC
Reel/Frame 068985/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2021
From: NAHLUS, IHAB; ENGELHARDT, MARC R.; KEYSE, MARK R.
To: DELPHI TECHNOLOGIES IP LIMITED
Reel/Frame 057330/0480 →
Continuity (1)
Related Publication 20230062191A1 · Mar 2, 2023