Protective layer over FinFET and method of forming same

1. A method, comprising:

forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin comprising different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width;

forming a first capping layer over the first fin;

forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness; and

forming a first dielectric layer over the first capping layer and a second dielectric layer over the second capping layer, wherein forming the first dielectric layer comprises converting an entirety of the first capping layer to a first intermediate layer, and wherein forming the second dielectric layer comprises converting an upper portion of the second capping layer to a second intermediate layer with a lower portion of the second capping layer remaining unconverted.

2. The method of claim 1 , wherein the forming the first capping layer and the forming the second capping layer are performed simultaneously.

3. The method of claim 1 , wherein the first fin comprises silicon, and wherein the second fin comprises silicon-germanium.

4. The method of claim 3 , wherein the second thickness is greater than the first thickness.

5. The method of claim 1 further comprising, after forming the first fin and the second fin, trimming the first fin and the second fin.

6. The method of claim 5 , wherein after trimming the first fin and the second fin, the first fin has a third width and the second fin has a fourth width, and wherein a difference between the fourth width and the second width is greater than a difference between the third width and the first width.

7. The method of claim 6 , wherein after forming the first capping layer and the second capping layer, the first fin and the first capping layer have a fifth width and the second fin and the second capping layer have a sixth width, and wherein the fifth width is the same as the sixth width.

8. A method, comprising:

forming a structure comprising a plurality of fins within a dielectric material over a substrate, the plurality of fins comprising a first fin, a second fin, a first dummy fin, and a second dummy fin, the first fin and the second fin comprising different materials;

forming isolation regions from the dielectric material between each of the plurality of fins, the first fin and the first dummy fin being separated by a first opening, the second fin and the second dummy fin being separated by a second opening;

expanding the first opening and expanding the second opening;

performing a first reduction of the first opening and the second opening, wherein the first reduction comprises forming a first capping layer over the first fin and a second capping layer over the second fin, wherein a thickness of the first capping layer is lesser than a thickness of the second capping layer;

performing a second reduction of the first opening and the second opening, wherein the second reduction comprises forming a first dielectric layer over the first capping layer, a first dummy dielectric layer over the first dummy fin, a second dielectric layer over the second capping layer, and a second dummy dielectric layer over the second dummy fin, wherein a combined thickness of the first capping layer and the first dielectric layer is greater than a thickness of the first dummy dielectric layer; and

forming gate structures over the first fin and the second fin.

9. The method of claim 8 , wherein a first amount of the expanding the first opening is lesser than a second amount of the expanding the second opening.

10. The method of claim 9 , wherein a difference between the thickness of the first capping layer and the first amount is the same as a difference between the thickness of the second capping layer and the second amount.

11. The method of claim 8 , wherein forming the first dielectric layer comprises forming a first partial layer and converting a portion of the first capping layer to a first intermediate layer, and wherein forming the second dielectric layer comprises forming a second partial layer and converting a first portion of the second capping layer to a second intermediate layer.

12. The method of claim 11 , wherein after forming the first dielectric layer and the second dielectric layer, the first dielectric layer physically contacts the first fin.

13. The method of claim 8 , wherein after forming the first capping layer and the second capping layer, a portion of the first capping layer extends directly over a first one of the isolation regions by a first extension distance, and a second portion of the second capping layer extends directly over a second one of the isolation regions by a second extension distance, the first extension distance being greater than the second extension distance.

14. The method of claim 8 , wherein forming the first capping layer and the second capping layer further comprises forming discontinuous nodules directly on the first dummy fin and the second dummy fin.

15. A method, comprising:

forming a plurality of fins over a substrate, the plurality of fins comprising a first fin, a second fin, and a dielectric fin;

forming an isolation region interposed between the first fin and the second fin, the isolation region being interposed between the dielectric fin and the substrate;

depositing a semiconductor material, depositing the semiconductor material comprising forming a first semiconductor layer over the first fin, a second semiconductor layer over the second fin, and a third semiconductor layer over the dielectric fin, wherein the first fin is free of the second semiconductor layer and the third semiconductor layer, wherein the second fin is free of the first semiconductor layer and the third semiconductor layer, and wherein the dielectric fin is free of the first semiconductor layer and the second semiconductor layer;

forming an oxide layer over the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and

forming a gate structure over the oxide layer.

16. The method of claim 15 , wherein depositing the semiconductor material comprises depositing silicon at temperatures between about 500° C. and about 750° C.

17. The method of claim 15 , wherein the third semiconductor layer is amorphous.

18. The method of claim 15 , wherein the first fin is a silicon fin, and wherein the second fin is a silicon germanium fin.

19. The method of claim 15 , wherein a thickness of the first semiconductor layer is greater than a thickness of the third semiconductor layer.

20. The method of claim 15 , wherein the first semiconductor layer and the second semiconductor layer have a higher crystallinity than the third semiconductor layer.