BFLOAT16 scale and/or reduce instructions
Techniques for scale and reduction of BF16 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.
1. An apparatus comprising:
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of an exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand; and
the execution circuitry to execute the decoded instruction according to the opcode.
2. The apparatus of claim 1 , wherein the field for the identification of the first source operand is to identify a vector register.
3. The apparatus of claim 1 , wherein the field for the identification of the first source operand is to identify a memory location.
4. The apparatus of claim 1 , wherein the execution circuitry is to use a round to nearest even rounding mode during execution of the decoded instruction.
5. The apparatus of claim 1 , wherein the floor value is a zero when the data element of the second packed data source is a denormal.
6. The apparatus of claim 1 , wherein the data element of the first packed data source is a zero when the data element of the first packed data source is a denormal.
7. The apparatus of claim 1 , wherein the instruction is to further include one or more fields for a writemask register.
8. A system comprising:
memory to store an instance of a single instruction;
decode circuitry to decode the instance of the single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of an exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand; and
the execution circuitry to execute the decoded instruction according to the opcode.
9. The system of claim 8 , wherein the field for the identification of the first source operand is to identify a vector register.
10. The system of claim 8 , wherein the field for the identification of the first source operand is to identify a memory location.
11. The system of claim 8 , wherein the execution circuitry is to use a round to nearest even rounding mode during execution of the decoded instruction.
12. The system of claim 8 , wherein the floor value is a zero when the data element of the second packed data source is a denormal.
13. The system of claim 8 , wherein the instruction is to further include one or more fields for a writemask register.
14. The system of claim 8 , wherein the data element of the first packed data source is a zero when the data element of the first packed data source is a denormal.
15. A non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction is to be processed by a processor by performing a method comprising:
decoding the instance of the single instruction, the single instruction having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of an exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand; and
executing the decoded instruction according to the opcode.
16. The non-transitory machine-readable medium of claim 15 , wherein the field for the identification of the first source operand is to identify a vector register.
17. The non-transitory machine-readable medium of claim 15 , wherein the field for the identification of the first source operand is to identify a memory location.
18. The non-transitory machine-readable medium of claim 15 , wherein the executing is to use a round to nearest even rounding mode during execution of the decoded instruction.
19. The non-transitory machine-readable medium of claim 15 , wherein the floor value is a zero when the data element of the second packed data source is a denormal.
20. The non-transitory machine-readable medium of claim 15 , wherein the instruction is to further include one or more fields for a writemask register.
21. The non-transitory machine-readable medium of claim 15 , wherein the data element of the first packed data source is a zero when the data element of the first packed data source is a denormal.
22. A non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction is to be processed by a processor by performing a method comprising:
translating the particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture, the particular single instruction having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of an exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand;
decoding the one or more instructions of a second, different instruction set architecture;
executing the decoded one or more instructions of a second, different instruction set architecture.
23. The non-transitory machine-readable medium of claim 22 , wherein the field for the identification of the first source operand is to identify a vector register.
24. The non-transitory machine-readable medium of claim 22 , wherein the field for the identification of the first source operand is to identify a memory location.
25. The non-transitory machine-readable medium of claim 22 , wherein the executing is to use a round to nearest even rounding mode during execution of the decoded instruction.
26. The non-transitory machine-readable medium of claim 22 , wherein the floor value is a zero when the data element of the second packed data source is a denormal.
27. The non-transitory machine-readable medium of claim 22 , wherein the data element of the first packed data source is a zero when the data element of the first packed data source is a denormal.
28. The non-transitory machine-readable medium of claim 22 , wherein the instruction is to further include one or more fields for a writemask register.
29. A method comprising:
translating a particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture, the particular single instruction to include fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of an exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand;
decoding the one or more instructions of a second, different instruction set architecture;
executing the decoded one or more instructions of a second, different instruction set architecture.
30. The method of claim 29 , wherein the field for the identification of the first source operand is to identify a vector register.
31. The method of claim 29 , wherein the field for the identification of the first source operand is to identify a memory location.
32. The method of claim 29 , wherein the executing is to use a round to nearest even rounding mode during execution of the decoded instruction.
33. The method of claim 29 , wherein the floor value is a zero when the data element of the second packed data source is a denormal.
34. The method of claim 29 , wherein the instruction is to further include one or more fields for a writemask register.
35. The method of claim 29 , wherein the data element of the first packed data source is a zero when the data element of the first packed data source is a denormal.