IP Library Granted Patent US 12,116,002
Granted Patent B2
US 12,116,002 · App. 17/466,359 · Granted Oct 15, 2024

Information processing apparatus, information processing method, and recording medium

Inventors: Hiroyuki Wada (Kyoto, JP); Yoshiharu Imamoto (Kanagawa, JP); Toru Iwano (Osaka, JP); Takayuki Fujii (Osaka, JP)
Assignee: PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
B60W50/029B60W50/0205G06F9/45558G06F21/554G06F21/74G06F2009/45587G06F2221/034
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,116,002
App. No.
17/466,359
Granted
Oct 15, 2024
Kind
B2
Abstract

An information processing apparatus includes: a communication device that communicates with an external apparatus outside the information processing apparatus; a memory that includes a protected region and an unprotected region; a processor that operates in a first mode and a second mode, the first mode being a mode in which access to the protected region and access to the unprotected region are allowed, the second mode being a mode in which access to the protected region is prohibited and access to the unprotected region is allowed; a first device controller that controls the communication device by the processor operating in the first mode; a virtual machine manager that causes one or more virtual machines to operate by the processor operating in the second mode; and a second device controller that controls the communication device by the processor operating in the second mode.

Claims (46)

1. An information processing apparatus, comprising:

a device that communicates with an external apparatus, the external apparatus being outside the information processing apparatus;

a memory that includes a protected region and an unprotected region;

a processor that operates in a first mode and a second mode, the first mode allowing access to the protected region of the memory and allowing access to the unprotected region of the memory, the second mode prohibiting access to the protected region of the memory and allowing access to the unprotected region of the memory;

a first controller that controls the device in response to the processor operating in the first mode;

a virtual machine manager that is a hypervisor, the hypervisor causing one or more virtual machines to operate in response to the processor operating in the second mode; and

a second controller that controls the device in response to the processor operating in the second mode.

2. The information processing apparatus according to claim 1 , further comprising:

a switch that switches, in response to the processor operating in the first mode, control of the device from control by the second controller to control by the first controller.

3. The information processing apparatus according to claim 2 , further comprising:

a monitor that, in response to the processor operating in the first mode, monitors a region of the memory as a monitoring target, and determines whether the monitoring target has an anomaly, the region being allocated to the virtual machine manager,

wherein, when the monitor determines that the monitoring target has an anomaly, the switch switches control of the device, when the monitor communicates with the external apparatus, from the control by the second controller to the control by the first controller.

4. The information processing apparatus according to claim 2 ,

wherein the switch further performs control to prohibit the control of the device by the second controller when the switch switches from the control by the second controller to the control by the first controller.

5. The information processing apparatus according to claim 1 ,

wherein the first controller controls the device using a first device region included in the protected region of the memory, and

the second controller controls the device using a second device region included in the unprotected region of the memory.

6. The information processing apparatus according to claim 1 ,

wherein the first controller controls the device using a second device region included in the unprotected region of the memory, and

the second controller controls the device using the second device region of the memory.

7. The information processing apparatus according to claim 1 , further comprising:

an application that, in response to the processor operating in the second mode, performs predetermined processing and adds a digital signature to data that the application is to transmit to the external apparatus; and

a signature verifier that, in response to the processor operating in the first mode, receives the data to which the application has added the digital signature, and transmits the data to the external apparatus when the digital signature is successfully verified.

8. The information processing apparatus according to claim 1 , further comprising:

an application that, in response to the processor operating in the second mode, performs predetermined processing and generates one or more data items that the application is to transmit to the external apparatus; and

a behavior verifier that, in response to the processor operating in the first mode, receives the one or more data items generated by the application, obtains, from the protected region of the memory, an appropriate behavior condition defining appropriate behavior of the application concerning communication, and when the behavior verifier determines that at least one data item out of the one or more data items satisfies the appropriate behavior condition, transmits the at least one data item to the external apparatus.

9. The information processing apparatus according to claim 2 , further comprising:

a vehicle controller that controls a vehicle,

wherein, when the switch switches from the control by the second controller to the control by the first controller, the vehicle controller obtains, from the protected region of the memory, control information for fallback control of the vehicle, and controls the vehicle in accordance with the control information obtained from the protected region of the memory.

10. The information processing apparatus according to claim 1 ,

wherein the processor switches between operation in the first mode and operation in the second mode in a time-sharing manner.

11. The information processing apparatus according to claim 1 ,

wherein the processor includes a plurality of cores,

at least one of the plurality of cores operates in the first mode, and

at least one of the plurality of cores that is not operating in the first mode operates in the second mode.

12. The information processing apparatus according to claim 1 ,

wherein the information processing apparatus is an electronic control unit (ECU) provided in a vehicle.

13. An information processing method executed by an information processing apparatus, the information processing apparatus including:

a device that communicates with an external apparatus, the external apparatus being outside the information processing apparatus;

a memory that includes a protected region and an unprotected region; and

a processor that operates in a first mode and a second mode, the first mode allowing access to the protected region of the memory and allowing access to the unprotected region of the memory, the second mode prohibiting access to the protected region of the memory and allowing access to the unprotected region of the memory,

the information processing method comprising:

controlling a first controller to control the device in response to the processor operating in the first mode;

causing a virtual machine manager, which is hypervisor, to cause one or more virtual machines to operate in response to the processor operating in the second mode; and

controlling a second controller to control the device in response to the processor operating in the second mode.

14. A non-transitory computer-readable recording medium having recorded thereon a program that causes a computer to execute the information processing method according to claim 13 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
Reel/Frame 066709/0702 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2022
From: WADA, HIROYUKI; IMAMOTO, YOSHIHARU; IWANO, TORU; FUJII, TAKAYUKI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 059628/0839 →
Priority Claims (1)
JP 2020-154123 · Sep 14, 2020 · national
Continuity (1)
Related Publication 20220080989A1 · Mar 17, 2022