Parasitic insensitive sampling in sensors

1. A sensor system subject to a variable parasitic capacitance, the sensor system comprising:

a sensor comprising a sense capacitor with a variable sense capacitance, wherein when an input pressure is sensed by the sensor, the variable sense capacitance is modulated, thereby generating one or more digital output signals indicative of the input pressure;

a readout circuit comprising a converter having an analog input connected to the sense capacitor, and

an offset capacitor operatively charged and discharged out of phase with respect to the sense capacitor;

wherein:

the sensor system uses the offset capacitor, based on an auto-zeroing technique, to sample the analog input of the converter prior to a charging phase of the sensor system so that some effects of the variable parasitic capacitance on the one or more digital output signals are reduced.

2. The sensor system of claim 1 , further comprising a feedback capacitor, and wherein the offset capacitor is configured to center variations of the sense capacitor to a center of a full-scale of the converter, the full-scale of the converter being set by the feedback capacitor.

3. The sensor system of claim 2 , wherein the feedback capacitor and the sense capacitor are configured, based on the auto-zeroing technique, to sample the analog input of the converter prior to the charging phase of the sensor system, thereby reducing the effects of the variable parasitic capacitance on the one or more digital output signals.

4. The sensor system of claim 3 , further comprising an integrator including an operational amplifier and integration capacitor, an operational amplifier input being connected to the analog input of the converter.

5. The sensor system of claim 4 , configured to receive a plurality of reference voltages and further comprising a switching arrangement being controlled by a plurality of clock signals to connect/disconnect the sense capacitor, the offset capacitor, and the feedback capacitor to/from corresponding reference voltages of the plurality of reference voltages.

6. The sensor system of claim 5 , wherein the plurality of clock signals comprises clock signals that are generated based on the one or more digital output signals.

7. The sensor system of claim 6 , wherein:

in the charging phase:

the switching arrangement is configured such that the plurality of reference voltages are sampled to store charges across the sense capacitor, the offset capacitor and the feedback capacitor; and

in an integration phase:

a combination of the charges stored on the sense capacitor, the offset capacitor and the feedback capacitor during the charging phase is transferred to an integrating capacitor, thereby generating an integrator output signal in correspondence of the input pressure.

8. The sensor system of claim 7 , wherein the plurality of clock signals have clock periods substantially smaller than a time during which the variable parasitic capacitance varies by one pF.

9. The sensor system of claim 7 , wherein the plurality of clock signals have clocks rates in the range of hundreds of KHz and the variable parasitic capacitance varies within a range of tens of pf and having a rate of change within a range of tens of pF/msec.

10. The sensor system of claim 5 , wherein the switching arrangement comprises metal-oxide semiconductor field-effect (MOSFET) transistors.

11. The sensor system of claim 1 , wherein the sense capacitor is serially connected with the analog input of the converter.

12. The sensor system of claim 1 , wherein the converter comprises a sigma-delta modulator.

13. The sensor system of claim 12 , wherein the sigma-delta modulator is a multi-stage noise shaping (MASH) modulator comprising one or more integrators interconnected with one or more comparators.

14. The sensor system of claim 1 , wherein the sensor is a MEMS sensor.

15. The sensor system of claim 1 , further comprising a gel material configured to transfer sensed pressure to the readout integrated circuit.

16. The sensor system of claim 15 , wherein the sensor is connected to the readout integrated circuit via bondwires that are exposed to the gel material.

17. A method of measuring pressure in presence of a variable parasitic capacitor, the method comprising:

providing a sense capacitor with a variable sense capacitance;

providing an offset capacitor;

providing a readout circuit having an integrating capacitor;

in an initial state

configuring the offset capacitor to sample, based on an auto-zeroing techniques, an output of the readout circuit to compensate for the parasitic capacitance;

in a charging phase following the initial state,

storing first charges across the sense capacitor; and

storing second charges across the offset capacitor;

in an integration phase, transferring the first and the second charges to the integrating capacitor, thereby generating a readout circuit output signal in correspondence of an input pressure, and

configuring the offset capacitor to center variations of the sense capacitor to a center of a full-scale of the readout circuit,

wherein the storing the first and the second charges and the transferring the first and the second charges are performed such that a charging and discharging of the offset capacitor is out of phase with respect to the sense capacitor.

18. The method of claim 17 , further comprising providing a feedback capacitor configured to:

set the full-scale of the readout circuit, and

during the initial phase, based on the auto-zeroing technique, sample an output of the readout circuit to compensate for the parasitic capacitance.

19. The method of claim 18 , wherein the sense capacitor is configured to sample, during the initial state, based on the auto-zeroing technique, the output of the readout circuit to compensate for the parasitic capacitance.