Composite interface circuit
Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R 1 ) with first direct current (“DC”) input current source having first voltage (V 1 ). First switching circuit includes first transistor (T 1 ) being coupled with first pull-up resistor (R 1 ) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T 2 ) being coupled by second pull-up resistor (R 2 ) with second DC input current source having second voltage (V 2 ). Second switching circuit further includes voltage divider coupling second transistor (T 2 ) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx 1 ) and first receiver conductor (Rx 1 ) of full duplex universal asynchronous data communication interface.
1. A composite interface circuit comprising a bidirectional single-conductor bus, for coupling together (a) a first full duplex universal asynchronous data communication interface (UArt 1 ) having a first operating voltage, the UArt 1 including a first receiver conductor (Rx 1 ) and a first transmitter conductor (Tx 1 ) and (b) a second full duplex universal asynchronous data communication interface (Uart 2 ) having a second operating voltage being independent of the first operating voltage, the UArt 2 including a second receiver conductor (Rx 2 ) and a second transmitter conductor (Tx 2 ), the composite interface circuit including:
the bidirectional single-conductor bus being coupled by a first pull-up resistor (R 1 ) with a first direct current (“DC”) input current source having a first voltage (V 1 );
a first switching circuit including a first transistor (T 1 ), the first transistor (T 1 ) being coupled with the first pull-up resistor (R 1 ) and with the bidirectional single-conductor bus;
a second switching circuit including a second transistor (T 2 ), the second transistor (T 2 ) being coupled by a second pull-up resistor (R 2 ) with a second DC input current source having a second voltage (V 2 ) being the first operating voltage of the UArt 1 , the second switching circuit further including a voltage divider coupling the second transistor (T 2 ) with the bidirectional single-conductor bus;
wherein the first switching circuit is configured for being coupled with a first transmitter conductor (Tx 1 ) of the UArt 1 ; and
wherein the second switching circuit is configured for being coupled with a first receiver conductor (Rx 1 ) of the UArt 1 .
2. The composite interface circuit of claim 1 , wherein the voltage divider includes a third resistor (R 3 ) and a fourth resistor (R 4 ), and wherein the third resistor (R 3 ) is coupled between the fourth resistor (R 4 ) and the bidirectional single-conductor bus, and wherein the second transistor (T 2 ) is coupled with the voltage divider at a first node between the third resistor (R 3 ) and the fourth resistor (R 4 ).
3. The composite interface circuit of claim 2 , wherein the voltage divider includes the third resistor (R 3 ) and the fourth resistor (R 4 ) as being selected for reducing the first voltage (V 1 ), at the first node, below a breakdown voltage of the second transistor (T 2 ).
4. The composite interface circuit of claim 1 , wherein the first voltage (V 1 ) is substantially higher than the second voltage (V 2 ).
5. The composite interface circuit of claim 1 , wherein the first voltage (V 1 ) is at least about one order of magnitude higher than the second voltage (V 2 ).
6. The composite interface circuit of claim 1 , wherein the first voltage (V 1 ) is selected as being substantially higher than the second voltage (V 2 ), and wherein the first pull-up resistor (R 1 ) is selected for causing the bidirectional single-conductor bus to be pulled up to a third voltage (V 3 ) being substantially higher than the second voltage (V 2 ) so as to substantially increase a rate of rise of a parasitic capacitance of the first transistor (T 1 ).
7. The composite interface circuit of claim 6 , wherein the first transistor (T 1 ) has a first switching voltage threshold; and wherein the third voltage (V 3 ) of the bidirectional single-conductor bus is pulled down to zero volts when a voltage on the first transmitter conductor (Tx 1 ) exceeds the first switching voltage threshold.
8. The composite interface circuit of claim 2 , wherein the first voltage (V 1 ) is selected as being substantially higher than the second voltage (V 2 ), and wherein the third resistor (R 3 ) and the fourth resistor (R 4 ) are selected for causing the first voltage (V 1 ) to be sufficiently divided at the first node so as to substantially increase a rate of rise of a parasitic capacitance of the second transistor (T 2 ) at the first node.
9. The composite interface circuit of claim 8 , wherein the second transistor (T 2 ) has a second switching voltage threshold; and wherein the third voltage (V 3 ) of the bidirectional single-conductor bus causes a fourth voltage (V 4 ) at a second node between the second transistor (T 2 ) and the second resistor (R 2 ) to be pulled down to zero volts when a voltage at the first node exceeds the second switching voltage threshold.
10. The composite interface circuit of claim 1 , further including the first full duplex universal asynchronous data communication interface (UArt 1 ) having the first operating voltage, and including a first receiver conductor (Rx 1 ) and a first transmitter conductor (Tx 1 ), wherein the first switching circuit is coupled with the first transmitter conductor (Tx 1 ), and wherein the second switching circuit is coupled with the first receiver conductor (Rx 1 ).
11. The composite interface circuit of claim 1 , further including:
another bidirectional single-conductor bus, being coupled by
a fifth pull-up resistor (R 5 ) with a third direct current (“DC”) input current source having a fifth voltage (V 5 );
a third switching circuit including a third transistor (T 3 ), the third transistor (T 3 ) being coupled with the fifth pull-up resistor (R 5 ) and with the another bidirectional single-conductor bus;
a fourth switching circuit including a fourth transistor (T 4 ), the fourth transistor (T 4 ) being coupled by a sixth pull-up resistor (R 6 ) with a fourth DC input current source having a sixth voltage (V 6 ) being the second operating voltage of the UArt 2 , the fourth switching circuit further including another voltage divider coupling the fourth transistor (T 4 ) with the another bidirectional single-conductor bus;
wherein the third switching circuit is configured for being coupled with a second transmitter conductor (Tx 2 ) of the UArt 2 ; and
wherein the fourth switching circuit is configured for being coupled with a second receiver conductor (Rx 2 ) of the UART 2 .
12. The composite interface circuit of claim 11 , wherein the another voltage divider includes a seventh resistor (R 7 ) and an eighth resistor (R 8 ), and wherein the seventh resistor (R 7 ) is coupled between the eighth resistor (R 8 ) and the another bidirectional single-conductor bus, and wherein the fourth transistor (T 4 ) is coupled with the another voltage divider at a third node between the seventh resistor (R 7 ) and the eighth resistor (R 8 ).
13. The composite interface circuit of claim 12 , wherein the another voltage divider includes the seventh resistor (R 7 ) and the eighth resistor (R 8 ) as being selected for reducing the fifth voltage (V 5 ), at the third node, below a breakdown voltage of the fourth transistor (T 4 ).
14. The composite interface circuit of claim 11 , wherein the fifth voltage (V 5 ) is substantially higher than the sixth voltage (V 6 ).
15. The composite interface circuit of claim 11 , wherein the fifth voltage (V 5 ) is at least about one order of magnitude higher than the sixth voltage (V 6 ).
16. The composite interface circuit of claim 11 , wherein the fifth voltage (V 5 ) is selected as being substantially higher than the sixth voltage (V 6 ), and wherein the fifth pull-up resistor (R 5 ) is selected for causing the another bidirectional single-conductor bus to be pulled up to a seventh voltage (V 7 ) being substantially higher than the sixth voltage (V 6 ) so as to substantially increase a rate of rise of a parasitic capacitance of the third transistor (T 3 ).
17. The composite interface circuit of claim 16 , wherein the third transistor (T 3 ) has a third switching voltage threshold; and wherein the seventh voltage (V 7 ) of the another bidirectional single-conductor bus is pulled down to zero volts when a voltage on the second transmitter conductor (Tx 2 ) exceeds the third switching voltage threshold.
18. The composite interface circuit of claim 12 , wherein the fifth voltage (V 5 ) is selected as being substantially higher than the sixth voltage (V 6 ), and wherein the seventh resistor (R 7 ) and the eighth resistor (R 8 ) are selected for causing the fifth voltage (V 5 ) to be sufficiently divided at the third node so as to substantially increase a rate of rise of a parasitic capacitance of the fourth transistor (T 4 ) at the third node.
19. The composite interface circuit of claim 18 , wherein the fourth transistor (T 4 ) has a fourth switching voltage threshold; and wherein the seventh voltage (V 7 ) of the another bidirectional single-conductor bus causes an eighth voltage (V 8 ) at a fourth node between the fourth transistor (T 4 ) and the second resistor (R 2 ) to be pulled down to zero volts when a voltage at the third node exceeds the fourth switching voltage threshold.
20. The composite interface circuit of claim 11 , further including the second full duplex universal asynchronous data communication interface (UArt 2 ) having the second operating voltage, and including a second receiver conductor (Rx 2 ) and a second transmitter conductor (Tx 2 ), wherein the third switching circuit is coupled with the second transmitter conductor (Tx 2 ), and wherein the fourth switching circuit is coupled with the second receiver conductor (Rx 2 ).