IP Library › Granted Patent US 12,009,349
Granted Patent B2
US 12,009,349 · App. 17/476,703 · Granted Jun 11, 2024

Vertical semiconductor package including horizontally stacked dies and methods of forming the same

Inventors: Jen-Yuan Chang (Hsinchu, TW); Chia-Ping Lai (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H01L25/105H01L25/50H01L24/06H01L24/29H01L24/30H01L25/0657H01L2224/06181H01L2224/2919H01L2224/30181H01L2225/06541
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Quick Facts
Patent No.
US 12,009,349
App. No.
17/476,703
Granted
Jun 11, 2024
Kind
B2
Abstract

A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Claims (47)

1. A semiconductor package comprising:

a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die back side that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side;

a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side; and

first dies disposed in a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines plane of the first die, and a first die interconnect structure disposed on the front side of the first semiconductor substrate and comprising a first die first connection line that is electrically connected to the first connection die interconnect structure,

wherein an angle formed between the plane of the first connection die and the plane of a first die in the first die stack ranges from about 45° to about 90°, and

wherein the plane of the first connection die is parallel to the plane of the second connection die.

2. The semiconductor package of claim 1 , wherein the first connection die interconnect structure electrically connects the first die first connection lines of at least two of the first dies directly to one another.

3. The semiconductor package of claim 1 , wherein the planes of the first dies are perpendicular to the planes of the first connection die and second connection die.

4. The semiconductor package of claim 1 , wherein:

the first dies comprise memory chips; and

the first connection die is a passive component.

5. The semiconductor package of claim 1 , wherein the first die stack comprises at least five of the first dies.

6. The semiconductor package of claim 1 , wherein:

the first die first connection lines are exposed on the first side of the first die stack.

7. The semiconductor package of claim 6 ,

wherein the first die interconnect structures each comprise a first die second connection line that is exposed on the second side of the first die stack and that is electrically connected to the second connection die interconnect structure.

8. The semiconductor package of claim 1 , further comprising:

second dies disposed in a second die stack disposed between the first connection die and the second connection die, each of the second dies comprising a second semiconductor substrate having a second die front side and an opposing second die backside that defines plane of the second die, and a second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die.

9. The semiconductor package of claim 8 , wherein a plane of a second die of the second die stack is parallel to the plane of the first connection die.

10. The semiconductor package of claim 8 , wherein a plane of a second die of the second die stack is perpendicular to the plane of the first connection die.

11. A semiconductor package comprising:

a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die backside that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side;

a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side;

first dies disposed in a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines a plane of the first die, and a first die interconnect structure disposed on the first die front side and comprising a first die first connection line that is exposed on the first side of the first die stack and electrically connected to the first connection die interconnect structure, and a first die second connection line that is exposed on the second side of the first die stack and electrically connected to the second connection die interconnect structure; and

second dies disposed on the first connection die in a second die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the second dies comprising a second semiconductor substrate having a second die front side and an opposing second die backside that defines a plane of the stacked second die, and second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die interconnect structure,

wherein the plane of a first die in the first die stack is perpendicular to the plane of the first connection die and the plane of the second connection die.

12. The semiconductor package of claim 11 , wherein the first dies are stacked in a direction parallel to the plane of the first connection die.

13. The semiconductor package of claim 11 , wherein the plane of a second die is parallel to the plane of the first connection die.

14. The semiconductor package of claim 11 , wherein the plane of each second die is perpendicular to the plane of the first connection die.

15. The semiconductor package of claim 11 , wherein:

the first connection die interconnect structure electrically connects the first die first connection lines of at least two of the first dies directly; and

the first connection die interconnect structure electrically connects the second die first connection lines of at least two of the second dies directly.

16. The semiconductor package of claim 11 , wherein:

the first dies and the second dies comprise memory chips; and

the first connection die is a passive component.

17. The semiconductor package of claim 11 , wherein

the second die first connection lines are exposed on the first side of the second die stack.

18. The semiconductor package of claim 17 ,

a second die second connection lines are exposed on the second side of the second die stack.

19. A semiconductor package comprising:

a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die backside that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side;

a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side; and

a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, the first die stack comprising first dies that are stacked on one another, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines plane of the first die, and a first die interconnect structure disposed on the first die front side, the first die interconnect structure comprising a first die first connection line that is electrically connected to the first connection die interconnect structure and a first die second connection line that is electrically connected to the second connection die interconnect structure,

wherein the plane of the first connection die is parallel to the plane of the second connection die, and

wherein the first dies are stacked in a direction parallel to the planes of the first connection die and the second connection die.

20. The semiconductor package of claim 19 , further comprising a second die stack having a second die first side that is bonded to the first connection die and an opposing second die second side that is bonded to the second connection die, the second die stack comprising second dies that are stacked on one another, each of the second dies comprising a second semiconductor substrate and a second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die interconnect structure,

wherein the second dies are stacked in a direction parallel to the planes of the first connection die and the second connection die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2021
From: CHANG, JEN-YUAN; LAI, CHIA-PING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 057500/0762 →
Continuity (2)
Provisional Application 63166371 · Mar 26, 2021
Related Publication 20220310570A1 · Sep 29, 2022
Cited By (1)
US 12,374,674