Method for forming a semiconductor device
A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.
1. A method for forming a semiconductor device, the method comprising:
forming a device layer stack on a substrate, the device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over a topmost one of the channel layers, wherein the top sacrificial layer and the lower sacrificial layers are silicon-germanium layers, wherein the top sacrificial layer is thicker than each lower sacrificial layer;
forming a sacrificial gate structure on the top sacrificial layer, the sacrificial gate structure extending across the device layer stack;
etching the top sacrificial layer while using the sacrificial gate structure as an etch mask to form a top sacrificial layer portion underneath the sacrificial gate structure;
forming a first spacer on opposite sidewalls of the sacrificial gate structure and on end surfaces of the top sacrificial layer portion;
etching the channel layers and lower sacrificial layers while using the sacrificial gate structure and the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions underneath the sacrificial gate structure;
etching the lower sacrificial layer portions to form recesses in the device layer stack on opposite sides of the sacrificial gate structure, while the first spacer masks the end surfaces of the top sacrificial layer portion; and
forming a second spacer in the recesses, comprising conformally depositing dielectric material and using an isotropic etch to etch the conformally deposited dielectric material such that end surfaces of the channel layer portions, including end surfaces of a topmost channel layer portion, are exposed on opposite sides of the sacrificial gate structure and the dielectric material remains in the recesses to form the second spacer.
2. A method according to claim 1 , further comprising, after forming the second spacer, forming source and drain regions by epitaxially growing semiconductor material on the exposed end surfaces of the channel layer portions.
3. A method according to claim 1 , further comprising, after forming the second spacer, forming a gate stack by replacing the sacrificial gate structure with a gate stack.
4. A method according to claim 1 , wherein the isotropic etch used while forming the second spacer is selective for the conformally deposited dielectric material rather than the material of the first spacer.
5. A method according to claim 1 , wherein the etching of the top sacrificial layer extends completely through the top sacrificial layer.
6. A method according to claim 5 , wherein the device layer stack further comprises an insulating interface layer between the top sacrificial layer and the topmost channel layer;
wherein while etching the top sacrificial layer, the insulating interface layer acts as an etch stop.
7. A method according to claim 1 , wherein the forming of the first spacer comprises conformally depositing a first spacer material and subsequently anisotropically etching the first spacer material such that the first spacer material is removed from horizontally oriented surfaces and remain on vertically oriented surfaces, the vertically oriented surfaces comprising both outer sidewalls of the device layer stack.
8. A method according to claim 1 , wherein the device layer stack is formed by a stack of nanowires or by a stack of nanosheets.
9. A method according to claim 1 , wherein the device layer stack is a first device layer stack formed on a first device region of the substrate and the method further comprises:
forming a second device layer stack on a second device region of the substrate, the second device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over a topmost one of the channel layers, wherein the top sacrificial layer and the lower sacrificial layers are silicon-germanium layers, wherein the top sacrificial layer is thicker than each lower sacrificial layer, the first and second device layer stacks being spaced apart by a trench filled with an insulating wall material to form an insulating wall;
forming a sacrificial gate structure extending across the first and second device layer stacks and the insulating wall;
etching the top sacrificial layer of the second device layer stack while using the sacrificial gate structure as an etch mask to form a top sacrificial layer portion underneath the sacrificial gate structure;
etching the channel layers and lower sacrificial layers of the second device layer stack while using the sacrificial gate structure and the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions underneath the sacrificial gate structure; and
etching the lower sacrificial layer portions to form recesses in the second device layer stack on opposite sides of the sacrificial gate structure, while the first spacer masks the end surfaces of the top sacrificial layer portions.
10. A method according to claim 9 , further comprising, after forming the second spacer, forming source and drain regions by epitaxially growing semiconductor material on the exposed end surfaces of the channel layer portions;
wherein the source and drain regions of the first device layer stack are n-doped and the source and drain regions of the second device layer stack are p-doped.
11. A method according to claim 9 , wherein the forming of the first spacer comprises conformally depositing a first spacer material and subsequently anisotropically etching the first spacer material such that the first spacer material is removed from horizontally oriented surfaces and remain on vertically oriented surfaces, the vertically oriented surfaces comprising an outer sidewall of each of the first and second device layer stacks.
12. A method according to claim 1 , wherein the lower sacrificial layers have a uniform thickness.
13. A method according to claim 9 , further comprising:
removing the sacrificial gate structure extending across the first and second device layer stacks and the insulating wall, to form a gate trench;
selectively removing lower and top sacrificial layer portions from the gate trench;
forming a gate stack in the gate trench, in the space left by removing the top sacrificial layer portion, the lower sacrificial layer portions and the sacrificial gate structure.
14. A method according to claim 13 , wherein, for each channel layer:
the gate stack abuts the channel layer on an upper side of the channel layer, on a lower side of the channel layer, and on a first lateral side of the channel layer, wherein a second lateral side of the channel layer is opposite to the first lateral side and abuts the insulating wall.
15. A method according to claim 1 , wherein the sacrificial gate structure comprises amorphous silicon.