IP Library Granted Patent US 11,837,520
Granted Patent B2
US 11,837,520 · App. 17/478,991 · Granted Dec 5, 2023

Semiconductor device and semiconductor device fabrication method

Inventor: Shinya Sasaki (Ebina, JP)
Assignee: FUJITSU LIMITED
H01L23/3675H01L21/568H01L23/3128H01L23/373H01L23/5383H01L25/0655H01L25/50
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Quick Facts
Patent No.
US 11,837,520
App. No.
17/478,991
Granted
Dec 5, 2023
Kind
B2
Abstract

The semiconductor device includes a first semiconductor IC, a second semiconductor IC with a smaller heat generation quantity than the first semiconductor IC, a first heat conduction member covering at least a portion of the first semiconductor IC, a second heat conduction member covering the second semiconductor IC and the first heat conduction member, and a heat dissipation member. The heat dissipation member covers the second heat conduction member and dissipates heat produced from the first semiconductor IC and second semiconductor IC to the exterior. A thermal conductivity of the first heat conduction member is lower than a thermal conductivity of the second heat conduction member in a horizontal direction, which is a direction in which the first semiconductor IC and the second semiconductor IC are arrayed.

Claims (35)

1. A semiconductor device comprising:

a first semiconductor IC;

a second semiconductor IC that is smaller in heat generation quantity than the first semiconductor IC;

a first heat conduction member disposed at an upper layer of at least a portion of the first semiconductor IC;

a second heat conduction member disposed at an upper layer of the second semiconductor IC and surrounding the first heat conduction member; and

a heat dissipation member disposed along a horizontal direction at an upper layer of the second heat conduction member, the horizontal direction being a direction in which the first semiconductor IC and the second semiconductor IC are arrayed,

wherein a thermal conductivity of the first heat conduction member is lower than a thermal conductivity in the horizontal direction of the second heat conduction member.

2. The semiconductor device according to claim 1 , wherein a thermal conductivity of the second heat conduction member in a height direction intersecting the horizontal direction is lower than the thermal conductivity thereof in the horizontal direction.

3. The semiconductor device according to claim 2 , wherein the thermal conductivity in the height direction of the second heat conduction member is lower than the thermal conductivity of the first heat conduction member.

4. The semiconductor device according to claim 3 , wherein a thickness of the second heat conduction member at the upper layer of the first heat conduction member is at most 1 mm.

5. The semiconductor device according to claim 1 , further comprising a sealing member that seals the first semiconductor IC and the second semiconductor IC, wherein

the first heat conduction member covers a surface of the first semiconductor IC that is exposed from the sealing member, and

the second heat conduction member covers a surface of the second semiconductor IC that is exposed from the sealing member.

6. The semiconductor device according to claim 2 , further comprising a sealing member that seals the first semiconductor IC and the second semiconductor IC, wherein

the first heat conduction member covers a surface of the first semiconductor IC that is exposed from the seating member, and

the second heat conduction member covers a surface of the second semiconductor IC that is exposed from the sealing member.

7. The semiconductor device according to claim 3 , further comprising a sealing member that seals the first semiconductor IC and the second semiconductor IC, wherein

the first heat conduction member covers a surface of the first semiconductor IC that is exposed from the sealing member, and

the second heat conduction member covers a surface of the second semiconductor IC that is exposed from the sealing member.

8. The semiconductor device according to claim 1 , further comprising a rewiring layer that electronically connects the first semiconductor IC and the second semiconductor IC.

9. The semiconductor device according to claim 2 , further comprising a rewiring layer that electronically connects the first semiconductor IC and the second semiconductor IC.

10. The semiconductor device according to claim 3 , further comprising a rewiring layer that electronically connects the first semiconductor IC and the second semiconductor IC.

11. The semiconductor device according to claim 1 , wherein the first semiconductor IC includes a substrate formed of monocrystalline silicon and the second semiconductor IC includes a substrate formed of a compound semiconductor.

12. The semiconductor device according to claim 2 , wherein the first semiconductor IC includes a substrate formed of monocrystalline silicon and the second semiconductor IC includes a substrate formed of a compound semiconductor.

13. The semiconductor device according to claim 3 , wherein the first semiconductor IC includes a substrate formed of monocrystalline silicon and the second semiconductor IC includes a substrate formed of a compound semiconductor.

14. The semiconductor device according to claim 1 , wherein the second heat conduction member is a graphite sheet.

15. The semiconductor device according to claim 2 , wherein the second heat conduction member is a graphite sheet.

16. The semiconductor device according to claim 3 , wherein the second heat conduction member is a graphite sheet.

17. A semiconductor device fabrication method comprising:

sealing a first semiconductor IC and a second semiconductor IC in a sealing member, the second semiconductor IC being smaller in heat generation quantity than the first semiconductor IC;

grinding the sealing member and causing surfaces of the first semiconductor IC and the second semiconductor IC to be exposed from the sealing member;

disposing a first heat conduction member at an upper layer of the first semiconductor IC exposed from the sealing member;

disposing a second heat conduction member at an upper layer of the second semiconductor IC exposed from the sealing member and surrounding the first heat conduction member; and

disposing a heat dissipation member along a horizontal direction at an upper layer of the second heat conduction member, the horizontal direction being a direction in which the first semiconductor IC and the second semiconductor IC are arrayed,

wherein a thermal conductivity of the first heat conduction member is lower than a thermal conductivity in the horizontal direction of the second heat conduction member.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2026
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 074197/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2021
From: SASAKI, SHINYA
To: FUJITSU LIMITED
Reel/Frame 057540/0066 →
Priority Claims (1)
JP 2020-214119 · Dec 23, 2020 · national
Continuity (1)
Related Publication 20220199487A1 · Jun 23, 2022