IP Library Granted Patent US 11,632,857
Granted Patent B2
US 11,632,857 · App. 17/480,696 · Granted Apr 18, 2023

Setting the impedance of signal traces of a circuit board using a reference trace

Inventors: Manhtien V. Phan (Morgan Hill, CA); Mau-Lin Chou (Milpitas, CA); Chih-Hao Lee (New Taipei, TW)
Assignee: SUPER MICRO COMPUTER, INC.
H05K1/0253H05K1/0298H05K2201/093
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Quick Facts
Patent No.
US 11,632,857
App. No.
17/480,696
Granted
Apr 18, 2023
Kind
B2
Abstract

A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.

Claims (12)

1. A circuit board comprising:

a dielectric layer;

a first signal trace and a second signal trace that are formed on a first surface of the dielectric layer on an edge connector of the circuit board;

a reference plane formed on a second surface of the dielectric layer; and

a reference trace formed within the dielectric layer and between the reference plane and the first and second signal traces, the reference trace being configured to set a differential impedance of the first and second signal traces,

wherein the reference plane, the reference trace, the first signal trace, and the second signal trace each comprises a metal.

2. The circuit board of claim 1 , wherein the differential impedance of the first and second signal traces is set to about 85 ohms.

3. The circuit board of claim 1 , wherein the reference trace has a width that is narrower than a spanning distance between outer side perimeters of the first signal trace and the second signal trace.

4. The circuit board of claim 1 , wherein the reference trace comprises copper.

5. The circuit board of claim 1 , wherein the reference trace has a first portion that is in parallel with the first and second signal traces and a second portion that is perpendicular to the first portion.

6. The circuit board of claim 1 , wherein the reference plane is between the dielectric layer and another layer of the circuit board.

7. The circuit board of claim 1 , wherein the first signal trace and the second signal trace are contact fingers on the edge connector of the circuit board.

Assignments (1)
SECURITY INTEREST Recorded Jan 20, 2026
From: SUPER MICRO COMPUTER, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 074447/0643 →
Continuity (3)
Division 17070167 · Oct 14, 2020
Continuation 16750686 · Jan 23, 2020
Related Publication 20220007501A1 · Jan 6, 2022