Semiconductor memory devices with diode-connected MOS
A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
1. A memory device, comprising:
a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line (WL), a gate control line, and a bit line (BL);
wherein each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor; and
wherein the first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
2. The memory device of claim 1 , wherein the first transistor is gated by the WL, the second transistor is gated by the gate control line, and the capacitor has a second terminal connected to the BL.
3. The memory device of claim 1 , wherein the common node is connected to a first source/drain terminal of the first diode-connected transistor.
4. The memory device of claim 3 , wherein the first diode-connected transistor is an n-type transistor, and wherein the first source/drain terminal is not connected to a gate terminal of the first diode-connected transistor, with a second source/drain terminal of the first diode-connected transistor connected to its gate terminal.
5. The memory device of claim 3 , wherein the first diode-connected transistor is a p-type transistor, and wherein the first source/drain terminal is connected to a gate terminal of the first diode-connected transistor, with a second source/drain terminal of the first diode-connected transistor not connected to its gate terminal.
6. The memory device of claim 1 , wherein each of the plurality of non-volatile memory cells further comprises a third transistor coupled in series between the first diode-connected transistor and the second transistor.
7. The memory device of claim 6 , wherein the common node is connected to a first source/drain terminal of the third transistor, with a second source/drain terminal of the third transistor connected to the first diode-connected transistor.
8. The memory device of claim 1 , wherein each of the plurality of non-volatile memory cells further comprises one or more second diode-connected transistors serially coupled to the first diode-connected transistor.
9. The memory device of claim 1 , wherein a gate terminal of the first diode-connected transistor is connected to one of the BL, WL, or gate control line.
10. A method for operating a memory device, comprising:
providing a plurality of memory cells, each of the plurality of memory cells comprising a first transistor, a second transistor, a third transistor, a diode-connected transistor, and a capacitor, wherein the first, second, third, and diode-connected transistor are coupled in series;
programming a first one of the plurality of memory cells by performing: (i) asserting one of a plurality of word lines (WLs) that is connected to a gate terminal of the first transistor of the first memory cell; (ii) asserting one of a plurality of first control lines (CL 1 ) that is connected to a gate terminal of the second transistor of the first memory cell; and (iii) applying a programming voltage on one of a plurality of bit lines (BLs) connected to the capacitor of the first memory cell; and
asserting one of a plurality of second control lines (CL 2 ) that is connected to a gate terminal of the third transistor of a second one of the plurality of memory cells, wherein the CL 1 also gates the second transistor of the second memory cell and the BL is also connected to the capacitor of the second memory cell.
11. The method of claim 10 , wherein one terminal of the capacitor is connected to a node between the second transistor and the third transistor and the other terminal of the capacitor is connected to a respective one of the BLs.
12. The method of claim 10 , wherein a voltage drop across the capacitor is determined based on a difference between a voltage applied to one of the CL 1 , WL, or BL and a threshold voltage of the third transistor.
13. The method of claim 10 , wherein each of the plurality of memory cells further comprises one or more second diode-connected transistors serially coupled to the diode-connected transistor.
14. The method of claim 10 , wherein the diode-connected transistor is an n-type transistor having a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is connected to a common node between the second transistor and third transistor, and wherein the first source/drain terminal is not connected to a gate terminal of the diode-connected transistor and the second source/drain terminal is connected to its gate terminal.
15. A memory device, comprising:
a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a third transistor, a first diode-connected transistor, and a capacitor;
wherein each of the plurality of non-volatile memory cells is operatively coupled to a word line (WL), a first control line, a second control line, and a bit line (BL);
wherein the first transistor, second transistor, third transistor, first diode-connected transistor are coupled in series; and
wherein the capacitor has a first terminal connected to a common node between the second transistor and the third transistor, and a second terminal connected to the BL.
16. The memory device of claim 15 , wherein the first transistor is gated by the WL, the second transistor is gated by the first control line that is also connected to a gate terminal of the first diode-connected transistor, and the third transistor is gated by the second control line.
17. The memory device of claim 15 , wherein each of the plurality of memory cells further comprises one or more second diode-connected transistors serially coupled to first the diode-connected transistor.
18. The memory device of claim 15 , wherein the first diode-connected transistor is an n-type transistor having a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal is connected to the common node through the third transistor, and wherein the first source/drain terminal is not connected to a gate terminal of the first diode-connected transistor and the second source/drain terminal is connected to its gate terminal.
19. The memory device of claim 15 , wherein the common node is connected to a first source/drain terminal of the third transistor, with a second source/drain terminal of the third transistor connected to the first diode-connected transistor.
20. The memory device of claim 15 , wherein a gate terminal of the first diode-connected transistor is connected to one of the BL, WL, or first control line.