NEURAL NETWORK ACCELERATOR SYSTEM FOR IMPROVING SEMANTIC IMAGE SEGMENTATION

1 . An apparatus comprising:

at least one memory;

instructions in the apparatus; and

processor circuitry to execute the instructions to:

transmit an input image to at least one of vision network circuitry and imaging network circuitry;

generate, by the vision network circuitry, a first output based on a first feature map of the input image being generated by image scaling circuitry;

generate, by the imaging network circuitry, a second output of the input image;

upscale the first output, by bottleneck extender circuitry, to a resolution based on the second output;

concatenate the first and second output to generate a concatenated output;

apply a convolution operation to the concatenated output; and

generate, by segmentation head circuitry, a pixel level segmentation class map from the concatenated output.

2 . The apparatus of claim 1 , wherein the first feature map of the input image is a downscaled feature map describing features of the input image.

3 . The apparatus of claim 1 , wherein the processor circuitry is to execute the instructions to quantize the input image based on differential pulse code modulation.

4 . The apparatus of claim 1 , wherein the processor circuitry is to execute the instructions to transmit the concatenated output to a decoder of the imaging network circuitry.

5 . The apparatus of claim 1 , wherein in response to receiving an imaging task, the processor circuitry is to execute the instructions to selectively transmit the input image to an encoder of the imaging network circuitry.

6 . The apparatus of claim 1 , wherein the processor circuitry is to execute the instructions to perform a spatially separable depthwise convolution and a pointwise convolution.

7 . The apparatus of claim 1 , wherein the first output is an encoded feature map of at least 256 channels, and the second output is a less than 128 channel encoded feature map corresponding to an at least 1280×720 resolution input.

8 . A non-transitory computer readable medium comprising instructions, which, when executed, cause processor circuitry to at least:

transmit an input image to at least one of vision network circuitry and imaging network circuitry;

generate, by the vision network circuitry, a first output based on a first feature map of the input image being generated by image scaling circuitry;

generate, by the imaging network circuitry, a second output of the input image;

upscale the first output, by bottleneck extender circuitry, to a resolution based on the second output;

concatenate the first and second output to generate a concatenated output;

apply a convolution operation to the concatenated output; and

generate, by segmentation head circuitry, a pixel level segmentation class map from the concatenated output.

9 . The non-transitory computer readable medium of claim 8 , wherein the first feature map of the input image is a downscaled feature map describing features of the input image.

10 . The non-transitory computer readable medium of claim 8 , further including digital pulse-width modulation encoding circuitry to quantize the input image based on differential pulse code modulation.

11 . The non-transitory computer readable medium of claim 8 , wherein the instructions, when executed, cause the processor circuitry to transmit the concatenated output to a decoder of the imaging network circuitry.

12 . The non-transitory computer readable medium of claim 8 , wherein the instructions, when executed, cause the processor circuitry to selectively transmit the input image to an encoder of the imaging network circuitry.

13 . The non-transitory computer readable medium of claim 8 , wherein the instructions, when executed, cause the processor circuitry to perform a spatially separable depthwise convolution and a pointwise convolution.

14 . The non-transitory computer readable medium of claim 8 , wherein the first output is an encoded feature map of at least 256 channels, and the second output is a less than 128 channel encoded feature map corresponding to an at least 1280×720 resolution input.

15 . An apparatus comprising:

means for transmitting an input image to at least one of vision network circuitry and imaging network circuitry;

means for generating, by the vision network circuitry, a first output based on a first feature map of the input image being generated by image scaling circuitry;

means for generating, by the imaging network circuitry, a second output of the input image;

means for upscaling the first output, by bottleneck extender circuitry, to a resolution based on the second output;

means for concatenating the first and second output to generate a concatenated output;

means for applying a convolution operation to the concatenated output; and

means for generating, by segmentation head circuitry, a pixel level segmentation class map from the concatenated output.

16 . The apparatus of claim 15 , wherein the first feature map of the input image is a downscaled feature map describing features of the input image.

17 . The apparatus of claim 15 , further including means for quantizing the input image based on differential pulse code modulation.

18 . The apparatus of claim 15 , further including means for transmitting the concatenated output to a decoder of the imaging network circuitry.

19 . The apparatus of claim 15 , further including means for selectively transmitting the input image to an encoder of the imaging network circuitry.

20 . The apparatus of claim 15 , further including means for performing a spatially separable depthwise convolution and a pointwise convolution.

21 . The apparatus of claim 15 , wherein the first output is an encoded feature map of at least 256 channels, and the second output is a less than 128 channel encoded feature map corresponding to an at least 1280×720 resolution input.

22 . An apparatus to perform semantic image segmentation comprising:

mode selecting circuitry to transmit an input image to at least one of vision network circuitry and imaging network circuitry,

the vision network circuitry to generate a first output based on a first feature map of the input image being generated by image scaling circuitry,

the imaging network circuitry to generate a second output of the input image;

bottleneck extender circuitry to:

upscale the first output to a resolution based on the second output;

concatenate the first and second output to generate a concatenated output; and

apply a convolution operation to the concatenated output; and

segmentation head circuitry to generate a pixel level segmentation class map from the concatenated output.

23 .- 35 . (canceled)