Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication
Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.
1. An integrated circuit structure, comprising:
a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon, wherein one of the plurality of conductive trench contact structures comprises a conductive tap structure protruding through the corresponding trench insulating layer;
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures, wherein one of the plurality of dielectric spacers is laterally adjacent to the conductive tap structure;
an interlayer dielectric material above the trench insulating layers, the plurality of dielectric spacers, and the gate insulating layers;
an opening in the interlayer dielectric material, the opening exposing the conductive tap structure of the one of the plurality of conductive trench contact structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.
2. The integrated circuit structure of claim 1 , wherein the opening further exposes a portion of the corresponding trench insulating layer.
3. The integrated circuit structure of claim 2 , wherein the opening further exposes a gate insulating layer of a neighboring one of the plurality of gate structures.
4. The integrated circuit structure of claim 1 , wherein the trench insulating layers and the gate insulating layers comprise a different material.
5. The integrated circuit structure of claim 4 , wherein the trench insulating layers comprise silicon carbide, and the gate insulating layers comprise silicon nitride.
6. The integrated circuit structure of claim 4 , wherein the trench insulating layers comprise silicon nitride, and the gate insulating layers comprise silicon carbide.
7. The integrated circuit structure of claim 1 ,
wherein the opening further exposes a portion of the one of the plurality of dielectric spacers.
8. The integrated circuit structure of claim 1 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.
9. The integrated circuit structure of claim 1 , wherein the conductive structure includes a conductive line.
10. A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon;
forming a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon, wherein one of the plurality of conductive trench contact structures comprises a conductive tap structure protruding through the corresponding trench insulating layer;
forming a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures, wherein one of the plurality of dielectric spacers is laterally adjacent to the conductive tap structure;
forming an interlayer dielectric material above the trench insulating layers, the plurality of dielectric spacers, and the gate insulating layers;
forming an opening in the interlayer dielectric material, the opening exposing the conductive tap structure of the one of the plurality of conductive trench contact structures; and
forming a conductive structure in the opening, the conductive structure in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.
11. The method of claim 10 , wherein the opening further exposes a portion of the corresponding trench insulating layer.
12. The method of claim 11 , wherein the opening further exposes a gate insulating layer of a neighboring one of the plurality of gate structures.
13. The method of claim 10 ,
wherein the opening further exposes a portion of the one of the plurality of dielectric spacers.
14. The method of claim 10 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.
15. The method of claim 10 , wherein the conductive structure includes a conductive line.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon, wherein one of the plurality of conductive trench contact structures comprises a conductive tap structure protruding through the corresponding trench insulating layer;
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures, wherein one of the plurality of dielectric spacers is laterally adjacent to the conductive tap structure;
an interlayer dielectric material above the trench insulating layers, the plurality of dielectric spacers, and the gate insulating layers;
an opening in the interlayer dielectric material, the opening exposing the conductive tap structure of the one of the plurality of conductive trench contact structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , further comprising:
a camera coupled to the board.
20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.