Array substrate and display panel
The present disclosure provides an array substrate and a display panel. The array substrate includes a base substrate and at least one signal line unit in a fan-out region of the base substrate. Each of the at least one signal line unit includes two first signal lines and one second signal line, and the two first signal lines and the one second signal line are respectively in different layers and extend in a same direction. A center line of an orthographic projection of the one second signal line on the base substrate overlaps with a center line of an orthographic projection of an interval region between the two first signal lines.
1. An array substrate, comprising a base substrate and at least one signal line unit on the base substrate, the array substrate comprising a fan-out region, and the at least one signal line unit being in the fan-out region, wherein
each of the at least one signal line unit comprises two first signal lines and one second signal line;
in each of the at least one signal line unit, the two first signal lines are in a same layer and extend along a same direction, and the one second signal line and the two first signal lines are in different layers and are insulated from each other; and
a center line of an orthographic projection of the one second signal line on the base substrate along an extending direction of the one second signal line overlaps with a center line of an orthographic projection of an interval region between the two first signal lines along an extending direction of the two first signal lines,
wherein the at least one signal line unit comprises a plurality of signal line units, and
in the fan-our region, in a direction from each of two edges of the fan-out region to a center of the fan-out region, the plurality of signal line units are sequentially arranged in the direction, and second signal lines of the plurality of signal line units are gradually reduced in line length along an extending direction thereof and are gradually reduced in line width.
2. The array substrate of claim 1 , wherein
in each of the at least one signal line unit, the orthographic projection of the one second signal line on the base substrate at least partially overlaps with the orthographic projections of the two first signal lines on the base substrate, respectively; and
an overlapping area between the orthographic projection of the one second signal line on the base substrate and the orthographic projections of one of the two first signal lines on the base substrate is the same as an overlapping area between the orthographic projection of the one second signal line on the base substrate and the orthographic projections of the other of the two first signal lines on the base substrate.
3. The array substrate of claim 2 , wherein
in each of the at least one signal line unit, the two first signal lines and the one second signal line each are a broken line; and
an overlapping width between the orthographic projection of the one second signal line on the base substrate and the orthographic projection of one of the two first signal lines on the base substrate is the same as an overlapping width between the orthographic projection of the one second signal line on the base substrate and the orthographic projection of the other of the two first signal lines on the base substrate.
4. The array substrate of claim 3 , wherein
the second signal lines of the plurality of signal line units in the fan-out region have a same line width.
5. The array substrate of claim 4 , wherein
the second signal lines each have a line width greater than the line width of one of the first signal lines and less than a total line width of two of the first signal lines.
6. The array substrate of claim 5 , wherein
the second signal line has a line width in a range from 4.8 μm to 5.0 μm.
7. The array substrate of claim 6 , wherein
orthographic projections of the plurality of signal line units on the base substrate do not overlap with each other; and
at least some of the first signal lines and the second signal lines in different signal line units of the plurality of signal line units extend along a same direction.
8. The array substrate of claim 7 , further comprising a display region, wherein
the fan-out region is adjacent to the display region and is at a side of the display region, and at least one pixel unit and at least one touch electrode are provided in the display region; and
the first signal line extends to the display region to be coupled to a corresponding pixel unit and serves as a data line of the corresponding pixel unit, and the second signal line extends to the display region to be coupled to a corresponding touch control electrode and serves as a touch control signal line of the corresponding touch control electrode.
9. The array substrate of claim 8 , further comprising an insulating layer between a layer where the second signal lines are located and a layer where the first signal lines are located along a direction perpendicular to the base substrate.
10. The array substrate of claim 9 , wherein
the insulating layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is on a side of the first sub-layer distal to the base substrate, and
the first sub-layer has a thickness in a range from 2000 nm to 2500 nm along a direction perpendicular to the base substrate, and the second sub-layer has a thickness in a range from 80 nm to 150 nm along the direction perpendicular to the base substrate.
11. The array substrate of claim 10 , wherein
the first sub-layer has a thickness of 2300 nm, and the second sub-layer has a thickness of 100 nm.
12. The array substrate of claim 11 , wherein
the first sub-layer has a dielectric constant in a range from 3 to 3.5, and the second sub-layer has a dielectric constant in a range from 6 to 7.5.
13. The array substrate of claim 12 , wherein
the first sub-layer has a dielectric constant of 3.25, and the second sub-layer has a dielectric constant of 7.
14. The array substrate of claim 13 , wherein
a material of the first sub-layer comprises an organic resin material, and a material of the second sub-layer comprises an inorganic insulating material.
15. The array substrate of claim 14 , wherein
the material of the first sub-layer comprises an acrylic material, and the material of the second sub-layer comprises one of silicon nitride or silicon oxynitride.
16. The array substrate of claim 1 , wherein
in each of the at least one signal line unit, voltage signals of opposite polarities are supplied to the two first signal lines.
17. A display panel, comprising the array substrate of claim 1 , and one or more integrated circuits for driving the array substrate.
18. The display panel of claim 17 , wherein
the one or more integrated circuits are coupled to corresponding pixel units and corresponding touch electrodes in the display region in the array substrate through the at least one signal line unit.
19. The display panel of claim 18 , wherein
in each of the at least one signal line unit, an orthographic projection of the one second signal line on the base substrate at least partially overlaps with orthographic projections of the two first signal lines on the base substrate, respectively; and
an overlapping area between the orthographic projection of the second signal line on the base substrate and the orthographic projections of one of the two first signal lines on the base substrate is the same as an overlapping area between the orthographic projection of the one second signal line on the base substrate and the orthographic projections of the other of the two first signal lines on the base substrate.