IP Library Granted Patent US 11,610,621
Granted Patent B1
US 11,610,621 · App. 17/486,871 · Granted Mar 21, 2023

Oxide semiconductor-based FRAM

Inventors: Shou-Zen Chang (Hsinchu, TW); Ming-Han Liao (Hsinchu, TW); Min-Cheng Chen (Hsinchu County, TW); Hiroshi Yoshida (Hsinchu, TW)
Assignee: Powerchip Semiconductor Manufacturing Corporation
G11C11/2275G11C11/2255G11C11/2257G11C11/2273H01L27/11507
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Quick Facts
Patent No.
US 11,610,621
App. No.
17/486,871
Granted
Mar 21, 2023
Kind
B1
Abstract

An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.

Claims (13)

1. An oxide semiconductor-based FRAM, comprising:

a substrate;

a write electrode on said substrate;

a ferroelectric dielectric layer on said write electrode;

an oxide semiconductor layer on said ferroelectric dielectric layer, wherein said write electrode, said ferroelectric dielectric layer and said oxide semiconductor layer constitute a ferroelectric capacitor;

a source and a drain respectively on said oxide semiconductor layer and spaced apart at a distance, wherein said source and said drain further connect respectively to a plate line and a bit line, and in a write operation, said write electrode applies a bias voltage and said plate line applies a reverse bias voltage to write data to said ferroelectric capacitor;

a gate insulating layer on said source, said drain and said oxide semiconductor layer; and

a word line on said gate insulating layer, wherein said word line, said oxide semiconductor layer, said ferroelectric dielectric layer and said write electrode overlap each other in a direction vertical to said substrate.

2. The oxide semiconductor-based FRAM of claim 1 , further comprising a protection layer on said gate insulating layer and between said word line and said gate insulating layer.

3. The oxide semiconductor-based FRAM of claim 1 , wherein said source and said drain are not overlapped said write electrode in said direction vertical to said substrate.

4. The oxide semiconductor-based FRAM of claim 1 , wherein a surface of said substrate comprises an insulating layer, and said write electrode is on said insulating layer.

5. The oxide semiconductor-based FRAM of claim 1 , wherein in a read operation, said bit line applies a read voltage to read data stored in said ferroelectric dielectric layer.

6. The oxide semiconductor-based FRAM of claim 5 , wherein in a read operation, said word line applies a supply voltage to open a channel in said oxide semiconductor layer, and said write electrode applies said supply voltage to adjust a threshold voltage of said channel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2021
From: CHANG, SHOU-ZEN; LIAO, MING-HAN; CHEN, MIN-CHENG; YOSHIDA, HIROSHI
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 057615/0902 →
Priority Claims (1)
TW 110133488 · Sep 9, 2021 · national
Cited By (1)
US 12,289,890