Methods for writing HDD metadata in NAND flash
A data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller is in communication with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to identify patterns and/or structures of metadata for the hard disk drive, perform one or more of the following to the metadata to tailor the metadata: data shaping, content aware decoding, adaptive data trimming, and/or adaptive metablock sizing, and write the tailored metadata to the non-volatile memory device. The metadata is at least one of repeatable run out metadata, positioning error signal metadata, adjacent track interference metadata, and/or emergency power off metadata.
1 . A data storage device, comprising:
a hard disk drive coupled to a printed circuit board;
a volatile memory device coupled to the printed circuit board;
a non-volatile memory device coupled to the printed circuit board;
a controller coupled to the printed circuit board, wherein the controller is in communication with the hard disk drive, the volatile memory device, and the non-volatile memory device, wherein the controller is configured to:
identify patterns and/or structures of metadata for the hard disk drive, wherein the patterns and/or structures of metadata comprises non-uniformly distributed data, data write speed requirements, and data endurance requirements;
perform one or more of the following to the metadata to tailor the metadata: data shaping, content aware decoding, adaptive data trimming, and/or adaptive metablock sizing; and
write the tailored metadata to the non-volatile memory device.
2 . The data storage device of claim 1 , wherein the metadata is at least one of repeatable run out (RRO) metadata, positioning error signal (PES) metadata, adjacent track interference (ATI) metadata, emergency power off (EPO) metadata, and/or metadata centered around one or more values.
3 . The data storage device of claim 2 , wherein the non-volatile memory device comprises single level cells (SLC) or triple level cells (TLC), and wherein the SLC comprises a first SLC trim and a second SLC trim.
4 . The data storage device of claim 3 , wherein the EPO metadata is stored in the first SLC trim.
5 . The data storage device of claim 4 , wherein the PES metadata and the ATI metadata are stored in the second SLC trim.
6 . The data storage device of claim 2 , wherein the RRO metadata is stored in TLC.
7 . The data storage device of claim 2 , wherein the tailoring comprises tailoring EPO metadata using a first single level cell (SLC) trim that has a first speed.
8 . The data storage device of claim 7 , wherein the tailoring comprises tailoring PES metadata or ATI metadata using a second SLC trim that has a second speed slower than the first speed.
9 . The data storage device of claim 8 , wherein the second SLC trim has a higher endurance than the first SLC trim.
10 . The data storage device of claim 2 , wherein writing the tailored EPO metadata comprises writing to a dual plane.
11 . The data storage device of claim 2 , wherein writing the tailored PES metadata or ATI metadata comprises writing to a single plane.
12 . The data storage device of claim 2 , wherein the tailoring comprises performing at least two of data shaping, adaptive data trimming, and/or adaptive metablock sizing to the PES metadata or the ATI metadata.
13 . The data storage device of claim 2 , wherein the tailoring comprises performing adaptive data trimming and adaptive metablock sizing to the EPO metadata.
14 . The data storage device of claim 2 , wherein the tailoring comprises performing data shaping and content aware decoding to the RRO metadata.
15 . A data storage device, comprising:
a printed circuit board;
one or more rotatable disks coupled to the printed circuit board;
a volatile memory device coupled to the printed circuit board;
a non-volatile memory device coupled to the printed circuit board; and
a controller coupled to the printed circuit board, such that the controller is in communication with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device, wherein the controller is configured to:
identify patterns and/or structures of positioning error signal (PES) metadata or adjacent track interference (ATI) metadata for a hard disk drive;
tailor the PES metadata or the ATI metadata using data shaping; and
write the tailored PES metadata or ATI metadata to single level cell (SLC) memory of the non-volatile memory device.
16 . The data storage device of claim 15 , wherein the controller comprises an error correction engine, and wherein the error correction engine is configured to execute the data shaping.
17 . The data storage device of claim 15 , wherein the tailoring comprises converting an input sequence having a number of programmed bits greater than a number of erased bits to an output sequence having a second number of programmed bits less than a second number of erased bits, and wherein the input sequence and the output sequence are equal in data size.
18 . A data storage device, comprising:
a printed circuit board;
one or more rotatable disks coupled to the printed circuit board;
a volatile memory device coupled to the printed circuit board;
a non-volatile memory means coupled to the printed circuit board; and
a controller coupled to the printed circuit board such that the controller is in communication with the one or more rotatable disks, the volatile memory device, and the non-volatile memory means, wherein the controller is configured to:
identify patterns and/or structures of repeatable run out (RRO) metadata for a hard disk drive;
tailor the RRO metadata using content aware decoding; and
write the tailored RRO metadata to triple level cell (TLC) memory of the non-volatile memory means.
19 . The data storage device of claim 18 , wherein the identified patterns and/or structures comprises at least one of:
sparse regions with zero padding;
regions with counter behavior;
regions with byte repetitions; and
regions with random data with non-uniform distribution.
20 . The data storage device of claim 19 , wherein the controller comprises a decoder, wherein the decoder is configured to:
receive the identified patterns and/or structures; and
predict one or more combinations of bits based on the received identified patterns and/or structures before decoding the RRO metadata.