Systems and methods for obfuscating a circuit design

1. A method for generating an integrated circuit (IC) chip design, comprising:

receiving, by a server, a plurality of electrical parameters of a system on chip (SoC) to be designed, wherein the plurality of electrical parameters are received on a data sheet;

receiving a plurality of physical parameters of the SoC on the data sheet;

generating a first design of the SoC according to the plurality of electrical parameters and the plurality of physical parameters;

receiving a plurality of test parameters for testing the first design;

testing, via a design verification tool, the first design by applying the plurality of test parameters to the first design;

receiving a second design of a second SoC;

coupling the second design to the first design to generate a first IC chip design; and

arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.

2. The method of claim 1 , further comprising:

accessing a first design file of the first IC chip design;

coupling a third design to the second design to generate a second IC chip design;

arranging the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle;

accessing a second design file of the second IC chip design;

sending the first and second design files via a computer network to a fabrication computing device for fabrication of the first and second IC chips on the shuttle.

3. The method of claim 1 , further comprising:

accessing a first design file of the first IC chip design;

sending the first design file via a computer network to a fabrication computing device for fabrication of the first IC chip on the shuttle.

4. The method of claim 3 , further comprising:

creating a third design of a third SoC;

coupling the third design to the second design to generate a second IC chip design; and

arranging the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle.

5. The method of claim 4 , further comprising:

accessing a second design file of the second IC chip design;

sending the second design file via a computer network to the fabrication computing device for fabrication of the second IC chip on the shuttle.

6. The method of claim 1 , wherein the shuttle is a substrate that is configured to be divided into a plurality of portions, wherein the plurality of portions include a first portion on which the first IC chip is fabricated based on the first IC chip design and includes a second portion on which a second IC chip is fabricated based on a second IC chip design.

7. The method of claim 1 , wherein the plurality of electrical parameters include names of components of the SoC, a number of components of the SoC, a location of each of the components within the first design, a maximum value of operation associated with one or more of the components, and a minimum value of operation associated with the one or more of the components.

8. The method of claim 1 , wherein first design is a block design and is configured according to the plurality of electrical parameters and the plurality of physical parameters.

9. The method of claim 1 , wherein the plurality of physical parameters include a number of pin ins of the SoC, a number of pin outs of the SoC, and use or lack of use of a clock signal pin on the SoC.

10. The method of claim 1 , wherein the first design is represented using a block including a plurality of components of the SoC and includes an indication of use or nonuse of a clock signal.

11. The method of claim 1 , wherein the first design includes a plurality of components, wherein the plurality of test parameters include a plurality of conditions for determining whether each of the plurality of components of the SoC passes or fails a test.

12. The method of claim 1 , wherein the plurality of test parameters include a plurality of maximum values and a plurality of minimum values for testing the first design of the SoC.

13. The method of claim 1 , wherein the design verification tool cannot be downloaded to a client device from the server.

14. The method of claim 1 , wherein said arranging the first IC chip design to be included on the shuttle includes indicating that the first IC chip design is to occupy a location on a substrate for fabrication of the first IC chip design.

15. A system comprising:

a processor configured to:

receive a plurality of electrical parameters of a system on chip (SoC) to be designed, wherein the plurality of electrical parameters are received on a data sheet;

receive a plurality of physical parameters of the SoC on the data sheet;

generate a first design of the SoC based on the plurality of electrical parameters and the plurality of physical parameters;

receive a plurality of test parameters for testing the first design;

test, using a design verification tool, the first design by applying the plurality of test parameters to the first design;

receive a second design of a second SoC;

couple the second design to the first design to generate a first integrated circuit (IC) chip design; and

arrange the first IC chip design to be included on a shuttle for fabricating a first IC chip; and

a memory device coupled to the processor.

16. The system of claim 15 , wherein the processor is configured to:

access a first design file of the first IC chip design;

couple a third design to the second design to generate a second IC chip design;

arrange the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle;

access a second design file of the second IC chip design;

send the first and second design files via a computer network to a fabrication computing device for fabrication of the first and second IC chips on the shuttle.

17. The system of claim 15 , wherein the processor is configured to:

access a first design file of the first IC chip design;

send the first design file via a computer network to a fabrication computing device for fabrication of the first IC chip on the shuttle.

18. The system of claim 17 , wherein the processor is configured to:

create a third design of a third SoC;

couple the third design to the second design to generate a second IC chip design; and

arrange the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle.

19. The system of claim 18 , wherein the processor is configured to:

access a second design file of the second IC chip design;

send the second design file via a computer network to the fabrication computing device for fabrication of the second IC chip on the shuttle.

20. A method for generating an integrated circuit (IC) chip design, comprising:

receiving, by a client device, a plurality of electrical parameters of a first system on chip (SoC) to be designed;

receiving a plurality of physical parameters of the first SoC;

generating a first design of the first SoC according to the plurality of physical parameters and the plurality of electrical parameters;

receiving a plurality of test parameters for testing the first design;

providing the plurality of test parameters via a computer network to a server for applying the plurality of test parameters to test the first design;

coupling a second design of a second SoC to the first design to generate a first IC chip design; and

providing the first IC chip design to be included on a shuttle for fabricating a first IC chip.

21. The method of claim 20 , further comprising:

coupling a third design to the second design to generate a second IC chip design;

providing the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle.

22. The method of claim 20 , further comprising:

receiving a third design of a third SoC;

coupling the third design to the second design to generate a second IC chip design; and

arranging the second IC chip design to be included on the shuttle for fabricating a second IC chip on the shuttle.