Storage and offset memory cells

1. An apparatus, comprising:

a plurality of sense amplifiers, wherein each sense amplifier is coupled to a respective plurality of storage memory cells via a respective first digit line and a respective plurality of offset memory cells via a respective second digit line; and

a respective plurality of access devices coupled to the respective plurality of offset memory cells and the respective second digit line,

wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values, wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values, and wherein the plurality of offset memory cells have a cumulative capacitance that is approximately equal to a capacitance of the first digit line.

2. The apparatus of claim 1 , further comprising a memory array including the plurality of sense amplifiers, wherein the plurality of sense amplifiers are located at an edge of the memory array.

3. The apparatus of claim 2 , wherein the first and second digit lines are associated with a section of the memory array at the edge of the memory array.

4. The apparatus of claim 1 , further comprising a memory array comprising the plurality of sense amplifiers, the respective plurality of storage memory cells, and the respective plurality of offset memory cells.

5. The apparatus of claim 1 , wherein each of the storage memory cells and each of the offset memory cells comprise a respective capacitor having a particular capacitance.

6. The apparatus of claim 1 , further comprising a controller coupled to the pluralities of access devices and configured to selectively couple at least one of the respective plurality of offset memory cells to the respective second digit line.

7. The apparatus of claim 1 , wherein each of the plurality of sense amplifiers is coupled to a respective transistor configured to couple the sense amplifier to the respective second digit line.

8. The apparatus of claim 1 , wherein at least one of the offset memory cells is permanently coupled to the respective second digit line.

9. A method, comprising:

selectively coupling a subset of memory cells of a first plurality of memory cells couplable to a first conductive line of a memory array,

wherein respective voltages held capacitively by the subset of memory cells do not correspond to data values, and

wherein a cumulative capacitance of the subset of memory cells is approximately equal to a capacitance of a second conductive line of the memory array;

sensing, using a sense amplifier coupled to the first and second conductive lines, a respective data value stored by each of a second plurality of memory cells coupled to the second conductive line; and

offsetting a voltage differential of the sense amplifier with a cumulative voltage held capacitively by the subset of memory cells, wherein offsetting the voltage differential comprises:

charging the subset of memory cells to the cumulative voltage;

capacitively holding the cumulative voltage by the subset of memory cells;

concurrent with sensing the data value, discharging the cumulative voltage from the subset of memory cells

isolating the subset of memory cells from a first digit line coupled to the sense amplifier; and

isolating the second plurality of memory cells from a second digit line coupled to the sense amplifier.

10. The method of claim 9 , wherein offsetting the voltage differential further comprises:

coupling the subset of memory cells to the second digit line; and

coupling the second plurality of memory cells to the first digit line.

11. An apparatus, comprising:

an array of memory cells, formed on a CMOS layer, comprising:

a plurality of storage memory cells coupled to a first conductive line, wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values;

a plurality of offset memory cells coupled to a plurality of word lines and selectively couplable to a second conductive line via activation of a plurality of vertical pillar access devices,

wherein the plurality of vertical pillar access devices are activated by application of a signal to the plurality of word lines,

wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values, and

wherein a cumulative capacitance of the plurality of offset memory cells offsets a capacitance of the first conductive line; and

a sense amplifier, formed in the CMOS layer, coupled to the first and second conductive lines; and

a controller coupled to the array and configured to:

cause application of the signal to the plurality of word lines to activate the plurality of vertical pillar access devices; and

cause the sense amplifier to sense a data value from plurality of storage memory cells concurrently with activation of the plurality of vertical pillar access devices.

12. The apparatus of claim 11 , wherein each of the plurality of storage memory cells is coupled to the first conductive line via a respective vertical pillar access device coupled to a respective word line of the array.

13. The apparatus of claim 11 , wherein the cumulative capacitance of the plurality of offset memory cells is approximately equal to the capacitance of the first conductive line.

14. A method, comprising:

selectively coupling a subset of memory cells of a first plurality of memory cells couplable to a first conductive line of a memory array by enabling word line drivers associated with the subset of memory cells,

wherein respective voltages held capacitively by the subset of memory cells do not correspond to data values, and

wherein a cumulative capacitance of the subset of memory cells is approximately equal to a capacitance of a second conductive line of the memory array;

sensing, using a sense amplifier coupled to the first and second conductive lines, a respective data value stored by each of a second plurality of memory cells coupled to the second conductive line; and

offsetting a voltage differential of the sense amplifier with a cumulative voltage held capacitively by the subset of memory cells, wherein offsetting the voltage differential comprises:

charging the subset of memory cells to the cumulative voltage;

capacitively holding the cumulative voltage by the subset of memory cells; and

concurrent with sensing the data value, discharging the cumulative voltage from the subset of memory cells.

15. An apparatus, comprising:

an array of memory cells, formed on a CMOS layer, comprising:

a plurality of storage memory cells coupled to a first conductive line, wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values; and

a plurality of offset memory cells coupled to a plurality of word lines and selectively couplable to a second conductive line via activation of a plurality of vertical pillar access devices,

wherein the plurality of vertical pillar access devices are activated by application of a signal to the plurality of word lines,

wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values,

wherein a cumulative capacitance of the plurality of offset memory cells offsets a capacitance of the first conductive line, and

wherein the plurality of storage memory cells and the plurality of offset memory cells have approximately a same respective capacitance; and

a sense amplifier, formed in the CMOS layer, coupled to the first and second conductive lines.